2021-09-13 07:57:45 +02:00
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#pragma once
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2021-02-17 02:00:59 +01:00
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/*
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2021-09-13 07:57:45 +02:00
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* ESP32_I2S_PARALLEL_DMA
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2021-02-17 02:00:59 +01:00
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*/
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#pragma once
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#if defined(ESP32) || defined(IDF_VER)
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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2021-09-30 00:20:16 +02:00
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#include <stdbool.h>
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#include <sys/types.h>
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#include <freertos/FreeRTOS.h>
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2021-09-13 07:57:45 +02:00
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#include <driver/i2s.h>
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2021-09-30 00:20:16 +02:00
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#include <esp_err.h>
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2022-01-03 20:12:30 +01:00
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//#include <esp32/rom/lldesc.h>
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//#include <esp32/rom/gpio.h>
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#include <rom/lldesc.h>
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#include <rom/gpio.h>
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2021-02-17 02:00:59 +01:00
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2021-09-13 07:57:45 +02:00
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// Get MCU Type and Max CLK Hz for MCU
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#include <esp32_i2s_parallel_mcu_def.h>
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2021-02-17 02:00:59 +01:00
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typedef enum {
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I2S_PARALLEL_WIDTH_8,
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I2S_PARALLEL_WIDTH_16,
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I2S_PARALLEL_WIDTH_24,
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I2S_PARALLEL_WIDTH_MAX
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} i2s_parallel_cfg_bits_t;
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typedef struct {
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int gpio_bus[24]; // The parallel GPIOs to use, set gpio to -1 to disable
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int gpio_clk;
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int sample_rate; // 'clockspeed'
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int sample_width;
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int desccount_a;
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lldesc_t * lldesc_a;
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int desccount_b; // only used with double buffering
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lldesc_t * lldesc_b; // only used with double buffering
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2021-02-19 10:08:15 +01:00
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bool clkphase; // Clock signal phase
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2022-01-04 12:06:40 +01:00
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bool int_ena_out_eof; // Do we raise an interrupt every time the DMA output loops? Don't do this unless we're doing double buffering!
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2021-02-17 02:00:59 +01:00
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} i2s_parallel_config_t;
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static inline int i2s_parallel_get_memory_width(i2s_port_t port, i2s_parallel_cfg_bits_t width) {
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switch(width) {
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case I2S_PARALLEL_WIDTH_8:
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2021-09-13 07:57:45 +02:00
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2022-01-04 12:06:40 +01:00
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#ifdef ESP32_ORIG
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2022-01-04 12:03:34 +01:00
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// Only I2S1 on the legacy ESP32 WROOM MCU supports space saving single byte 8 bit parallel access
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2021-02-17 02:00:59 +01:00
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if(port == I2S_NUM_1) {
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return 1;
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2022-01-04 12:03:34 +01:00
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} else {
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return 2;
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2022-01-04 12:06:40 +01:00
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}
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2021-09-13 07:57:45 +02:00
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#else
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2022-01-04 12:06:40 +01:00
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return 1;
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2021-09-13 07:57:45 +02:00
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#endif
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2021-02-17 02:00:59 +01:00
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case I2S_PARALLEL_WIDTH_16:
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return 2;
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case I2S_PARALLEL_WIDTH_24:
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return 4;
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default:
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return -ESP_ERR_INVALID_ARG;
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}
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}
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// DMA Linked List Creation
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void link_dma_desc(volatile lldesc_t *dmadesc, volatile lldesc_t *prevdmadesc, void *memory, size_t size);
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// I2S DMA Peripheral Setup Functions
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2022-01-04 12:06:40 +01:00
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esp_err_t i2s_parallel_driver_install(i2s_port_t port, i2s_parallel_config_t* conf);
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esp_err_t i2s_parallel_send_dma(i2s_port_t port, lldesc_t* dma_descriptor);
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esp_err_t i2s_parallel_stop_dma(i2s_port_t port);
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//i2s_dev_t* i2s_parallel_get_dev(i2s_port_t port);
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2021-02-17 02:00:59 +01:00
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// For frame buffer flipping / double buffering
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typedef struct {
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volatile lldesc_t *dmadesc_a, *dmadesc_b;
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int desccount_a, desccount_b;
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i2s_port_t i2s_interrupt_port_arg;
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} i2s_parallel_state_t;
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void i2s_parallel_flip_to_buffer(i2s_port_t port, int bufid);
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bool i2s_parallel_is_previous_buffer_free();
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2021-12-21 23:19:59 +01:00
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void i2s_parallel_set_previous_buffer_not_free();
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2021-02-17 02:00:59 +01:00
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// Callback function for when whole length of DMA chain has been sent out.
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typedef void (*callback)(void);
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void setShiftCompleteCallback(callback f);
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#ifdef __cplusplus
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}
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#endif
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#endif
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