571 lines
16 KiB
C++
571 lines
16 KiB
C++
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/*----------------------------------------------------------------------------/
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Lovyan GFX - Graphics library for embedded devices.
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Original Source:
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https://github.com/lovyan03/LovyanGFX/
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Licence:
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[FreeBSD](https://github.com/lovyan03/LovyanGFX/blob/master/license.txt)
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Author:
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[lovyan03](https://twitter.com/lovyan03)
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Contributors:
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[ciniml](https://github.com/ciniml)
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[mongonta0716](https://github.com/mongonta0716)
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[tobozo](https://github.com/tobozo)
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Modified heavily for the ESP32 HUB75 DMA library by:
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[mrfaptastic](https://github.com/mrfaptastic)
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/----------------------------------------------------------------------------*/
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static const char* TAG = "esp32_i2s_parallel_dma";
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#include <sdkconfig.h>
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#if defined (CONFIG_IDF_TARGET_ESP32)
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#include "esp32_i2s_parallel_dma.hpp"
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#include <driver/gpio.h>
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#include <driver/periph_ctrl.h>
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#include <soc/gpio_sig_map.h>
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#include <esp_err.h>
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#include <esp_log.h>
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/*
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callback shiftCompleteCallback;
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void setShiftCompleteCallback(callback f) {
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shiftCompleteCallback = f;
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}
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volatile int previousBufferOutputLoopCount = 0;
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volatile bool previousBufferFree = true;
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static void IRAM_ATTR irq_hndlr(void* arg) { // if we use I2S1 (default)
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SET_PERI_REG_BITS(I2S_INT_CLR_REG(ESP32_I2S_DEVICE), I2S_OUT_EOF_INT_CLR_V, 1, I2S_OUT_EOF_INT_CLR_S);
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previousBufferFree = true;
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} // end irq_hndlr
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*/
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static i2s_dev_t* getDev(int port)
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{
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#if defined (CONFIG_IDF_TARGET_ESP32S2)
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return &I2S0;
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#else
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return (port == 0) ? &I2S0 : &I2S1;
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#endif
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}
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void Bus_Parallel16::config(const config_t& cfg)
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{
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ESP_LOGI(TAG, "Performing config for ESP32 or ESP32-S2");
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_cfg = cfg;
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auto port = cfg.port;
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_dev = getDev(port);
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}
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//#if defined (CONFIG_IDF_TARGET_ESP32S2)
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static void _gpio_pin_init(int pin)
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{
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if (pin >= 0)
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{
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gpio_pad_select_gpio(pin);
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//gpio_hi(pin);
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gpio_set_direction((gpio_num_t)pin, GPIO_MODE_OUTPUT);
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gpio_set_drive_capability((gpio_num_t)pin, (gpio_drive_cap_t)3); // esp32s3 as well?
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}
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}
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bool Bus_Parallel16::init(void) // The big one that gets everything setup.
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{
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ESP_LOGI(TAG, "Performing DMA bus init() for ESP32 or ESP32-S2");
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if(_cfg.port < I2S_NUM_0 || _cfg.port >= I2S_NUM_MAX) {
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//return ESP_ERR_INVALID_ARG;
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return false;
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}
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if(_cfg.parallel_width < 8 || _cfg.parallel_width >= 24) {
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return false;
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}
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//auto freq = (_cfg.freq_write, 50000000u); // ?
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auto freq = (_cfg.bus_freq);
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uint32_t _clkdiv_write = 0;
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size_t _div_num = 10;
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// Calculate clock divider for ESP32-S2
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#if defined (CONFIG_IDF_TARGET_ESP32S2)
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static constexpr uint32_t pll_160M_clock_d2 = 160 * 1000 * 1000 >> 1;
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// I2S_CLKM_DIV_NUM 2=40MHz / 3=27MHz / 4=20MHz / 5=16MHz / 8=10MHz / 10=8MHz
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_div_num = std::min(255u, 1 + ((pll_160M_clock_d2) / (1 + _cfg.freq_write)));
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_clkdiv_write = I2S_CLK_160M_PLL << I2S_CLK_SEL_S
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| I2S_CLK_EN
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| 1 << I2S_CLKM_DIV_A_S
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| 0 << I2S_CLKM_DIV_B_S
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| _div_num << I2S_CLKM_DIV_NUM_S
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;
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#else
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// clock = 80MHz(PLL_D2_CLK)
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static constexpr uint32_t pll_d2_clock = 80 * 1000 * 1000;
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// I2S_CLKM_DIV_NUM 4=20MHz / 5=16MHz / 8=10MHz / 10=8MHz
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_div_num = std::min(255u, std::max(3u, 1 + (pll_d2_clock / (1 + freq))));
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_clkdiv_write = I2S_CLK_EN
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| 1 << I2S_CLKM_DIV_A_S
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| 0 << I2S_CLKM_DIV_B_S
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| _div_num << I2S_CLKM_DIV_NUM_S
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;
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#endif
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if(_div_num < 2 || _div_num > 16) {
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return false;
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}
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//ESP_LOGI(TAG, "i2s pll clk_div_main is: %d", _div_num);
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auto dev = _dev;
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volatile int iomux_signal_base;
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volatile int iomux_clock;
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int irq_source;
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// Initialize I2S0 peripheral
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if (_cfg.port == 0)
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{
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periph_module_reset(PERIPH_I2S0_MODULE);
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periph_module_enable(PERIPH_I2S0_MODULE);
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iomux_clock = I2S0O_WS_OUT_IDX;
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irq_source = ETS_I2S0_INTR_SOURCE;
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switch(_cfg.parallel_width) {
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case 8:
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case 16:
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iomux_signal_base = I2S0O_DATA_OUT8_IDX;
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break;
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case 24:
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iomux_signal_base = I2S0O_DATA_OUT0_IDX;
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break;
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default:
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return ESP_ERR_INVALID_ARG;
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}
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}
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#if !defined (CONFIG_IDF_TARGET_ESP32S2)
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// Can't compile if I2S1 if it doesn't exist with that hardware's IDF....
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else {
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periph_module_reset(PERIPH_I2S1_MODULE);
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periph_module_enable(PERIPH_I2S1_MODULE);
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iomux_clock = I2S1O_WS_OUT_IDX;
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irq_source = ETS_I2S1_INTR_SOURCE;
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switch(_cfg.parallel_width) {
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case 16:
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iomux_signal_base = I2S1O_DATA_OUT8_IDX;
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break;
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case 8:
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case 24:
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iomux_signal_base = I2S1O_DATA_OUT0_IDX;
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break;
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default:
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return ESP_ERR_INVALID_ARG;
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}
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}
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#endif
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// Setup GPIOs
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int bus_width = _cfg.parallel_width;
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// Clock output GPIO setup
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_gpio_pin_init(_cfg.pin_rd); // not used
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_gpio_pin_init(_cfg.pin_wr); // clock
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_gpio_pin_init(_cfg.pin_rs); // not used
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// Data output GPIO setup
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int8_t* pins = _cfg.pin_data;
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for(int i = 0; i < bus_width; i++)
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_gpio_pin_init(pins[i]);
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// Route clock signal to clock pin
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gpio_matrix_out(_cfg.pin_wr, iomux_clock, _cfg.invert_pclk, 0); // inverst clock if required
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for (size_t i = 0; i < bus_width; i++) {
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if (pins[i] >= 0) {
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gpio_matrix_out(pins[i], iomux_signal_base + i, false, false);
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}
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}
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// Setup i2s clock
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dev->sample_rate_conf.val = 0;
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// Third stage config, width of data to be written to IO (I think this should always be the actual data width?)
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dev->sample_rate_conf.rx_bits_mod = bus_width;
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dev->sample_rate_conf.tx_bits_mod = bus_width;
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dev->sample_rate_conf.rx_bck_div_num = 2;
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dev->sample_rate_conf.tx_bck_div_num = 2;
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// Clock configuration
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// dev->clkm_conf.val=0; // Clear the clkm_conf struct
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/*
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#if defined (CONFIG_IDF_TARGET_ESP32S2)
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dev->clkm_conf.clk_sel = 2; // esp32-s2 only
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dev->clkm_conf.clk_en = 1;
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#endif
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#if !defined (CONFIG_IDF_TARGET_ESP32S2)
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dev->clkm_conf.clka_en=0; // Use the 80mhz system clock (PLL_D2_CLK) when '0'
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#endif
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dev->clkm_conf.clkm_div_b=0; // Clock numerator
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dev->clkm_conf.clkm_div_a=1; // Clock denominator
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*/
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// Note: clkm_div_num must only be set here AFTER clkm_div_b, clkm_div_a, etc. Or weird things happen!
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// On original ESP32, max I2S DMA parallel speed is 20Mhz.
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//dev->clkm_conf.clkm_div_num = 32;
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dev->clkm_conf.val = _clkdiv_write;
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// I2S conf2 reg
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dev->conf2.val = 0;
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dev->conf2.lcd_en = 1;
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dev->conf2.lcd_tx_wrx2_en=0;
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dev->conf2.lcd_tx_sdx2_en=0;
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// I2S conf reg
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dev->conf.val = 0;
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#if defined (CONFIG_IDF_TARGET_ESP32S2)
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dev->conf.tx_dma_equal=1; // esp32-s2 only
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dev->conf.pre_req_en=1; // esp32-s2 only - enable I2S to prepare data earlier? wtf?
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#endif
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// Now start setting up DMA FIFO
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dev->fifo_conf.val = 0;
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dev->fifo_conf.rx_data_num = 32; // Thresholds.
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dev->fifo_conf.tx_data_num = 32;
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dev->fifo_conf.dscr_en = 1;
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#if !defined (CONFIG_IDF_TARGET_ESP32S2)
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// Enable "One datum will be written twice in LCD mode" - for some reason,
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// if we don't do this in 8-bit mode, data is updated on half-clocks not clocks
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if(_cfg.parallel_width == 8)
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dev->conf2.lcd_tx_wrx2_en=1;
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// Not really described for non-pcm modes, although datasheet states it should be set correctly even for LCD mode
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// First stage config. Configures how data is loaded into fifo
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if(_cfg.parallel_width == 24) {
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// Mode 0, single 32-bit channel, linear 32 bit load to fifo
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dev->fifo_conf.tx_fifo_mod = 3;
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} else {
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// Mode 1, single 16-bit channel, load 16 bit sample(*) into fifo and pad to 32 bit with zeros
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// *Actually a 32 bit read where two samples are read at once. Length of fifo must thus still be word-aligned
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dev->fifo_conf.tx_fifo_mod = 1;
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}
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// Dictated by ESP32 datasheet
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dev->fifo_conf.rx_fifo_mod_force_en = 1;
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dev->fifo_conf.tx_fifo_mod_force_en = 1;
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// Second stage config
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dev->conf_chan.val = 0;
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// 16-bit single channel data
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dev->conf_chan.tx_chan_mod = 1;
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dev->conf_chan.rx_chan_mod = 1;
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#endif
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// Reset FIFO
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dev->conf.rx_fifo_reset = 1;
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#if defined (CONFIG_IDF_TARGET_ESP32S2)
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while(dev->conf.rx_fifo_reset_st); // esp32-s2 only
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#endif
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dev->conf.rx_fifo_reset = 0;
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dev->conf.tx_fifo_reset = 1;
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#if defined (CONFIG_IDF_TARGET_ESP32S2)
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while(dev->conf.tx_fifo_reset_st); // esp32-s2 only
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#endif
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dev->conf.tx_fifo_reset = 0;
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// Reset DMA
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dev->lc_conf.in_rst = 1;
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dev->lc_conf.in_rst = 0;
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dev->lc_conf.out_rst = 1;
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dev->lc_conf.out_rst = 0;
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dev->lc_conf.ahbm_rst = 1;
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dev->lc_conf.ahbm_rst = 0;
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dev->in_link.val = 0;
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dev->out_link.val = 0;
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// Device reset
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dev->conf.rx_reset=1;
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dev->conf.tx_reset=1;
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dev->conf.rx_reset=0;
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dev->conf.tx_reset=0;
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dev->conf1.val = 0;
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dev->conf1.tx_stop_en = 0;
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/*
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// Allocate I2S status structure for buffer swapping stuff
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i2s_state = (i2s_parallel_state_t*) malloc(sizeof(i2s_parallel_state_t));
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assert(i2s_state != NULL);
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i2s_parallel_state_t *state = i2s_state;
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state->desccount_a = conf->desccount_a;
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state->desccount_b = conf->desccount_b;
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state->dmadesc_a = conf->lldesc_a;
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state->dmadesc_b = conf->lldesc_b;
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state->i2s_interrupt_port_arg = port; // need to keep this somewhere in static memory for the ISR
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*/
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dev->timing.val = 0;
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/*
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// We using the double buffering switch logic?
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if (conf->int_ena_out_eof)
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{
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// Get ISR setup
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esp_err_t err = esp_intr_alloc(irq_source,
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(int)(ESP_INTR_FLAG_IRAM | ESP_INTR_FLAG_LEVEL1),
|
||
|
|
irq_hndlr,
|
||
|
|
&state->i2s_interrupt_port_arg, NULL);
|
||
|
|
|
||
|
|
if(err) {
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
// Setup interrupt handler which is focussed only on the (page 322 of Tech. Ref. Manual)
|
||
|
|
// "I2S_OUT_EOF_INT: Triggered when rxlink has finished sending a packet"
|
||
|
|
// ... whatever the hell that is supposed to mean... One massive linked list? So all pixels in the chain?
|
||
|
|
dev->int_ena.out_eof = 1;
|
||
|
|
}
|
||
|
|
*/
|
||
|
|
|
||
|
|
|
||
|
|
#if defined (CONFIG_IDF_TARGET_ESP32S2)
|
||
|
|
ESP_LOGD(TAG, "init() GPIO and clock configuration set for ESP32-S2");
|
||
|
|
#else
|
||
|
|
ESP_LOGD(TAG, "init() GPIO and clock configuration set for ESP32");
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
void Bus_Parallel16::release(void)
|
||
|
|
{
|
||
|
|
if (_dmadesc_a)
|
||
|
|
{
|
||
|
|
heap_caps_free(_dmadesc_a);
|
||
|
|
_dmadesc_a = nullptr;
|
||
|
|
_dmadesc_count = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (_dmadesc_b)
|
||
|
|
{
|
||
|
|
heap_caps_free(_dmadesc_b);
|
||
|
|
_dmadesc_b = nullptr;
|
||
|
|
_dmadesc_count = 0;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void Bus_Parallel16::enable_double_dma_desc(void)
|
||
|
|
{
|
||
|
|
_double_dma_buffer = true;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Need this to work for double buffers etc.
|
||
|
|
bool Bus_Parallel16::allocate_dma_desc_memory(size_t len)
|
||
|
|
{
|
||
|
|
if (_dmadesc_a) heap_caps_free(_dmadesc_a); // free all dma descrptios previously
|
||
|
|
|
||
|
|
_dmadesc_count = len;
|
||
|
|
|
||
|
|
ESP_LOGI(TAG, "Allocating memory for %d DMA descriptors.", len);
|
||
|
|
|
||
|
|
_dmadesc_a= (HUB75_DMA_DESCRIPTOR_T*)heap_caps_malloc(sizeof(HUB75_DMA_DESCRIPTOR_T) * len, MALLOC_CAP_DMA);
|
||
|
|
|
||
|
|
if (_dmadesc_a == nullptr)
|
||
|
|
{
|
||
|
|
ESP_LOGE(TAG, "ERROR: Couldn't malloc _dmadesc_a. Not enough memory.");
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
if (_double_dma_buffer)
|
||
|
|
{
|
||
|
|
if (_dmadesc_b) heap_caps_free(_dmadesc_b); // free all dma descrptios previously
|
||
|
|
|
||
|
|
ESP_LOGD(TAG, "Allocating the second buffer (double buffer enabled).");
|
||
|
|
|
||
|
|
_dmadesc_b= (HUB75_DMA_DESCRIPTOR_T*)heap_caps_malloc(sizeof(HUB75_DMA_DESCRIPTOR_T) * len, MALLOC_CAP_DMA);
|
||
|
|
|
||
|
|
if (_dmadesc_b == nullptr)
|
||
|
|
{
|
||
|
|
ESP_LOGE(TAG, "ERROR: Couldn't malloc _dmadesc_b. Not enough memory.");
|
||
|
|
_double_dma_buffer = false;
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
_dmadesc_a_idx = 0;
|
||
|
|
_dmadesc_b_idx = 0;
|
||
|
|
|
||
|
|
ESP_LOGD(TAG, "Allocating %d bytes of memory for DMA descriptors.", sizeof(HUB75_DMA_DESCRIPTOR_T) * len);
|
||
|
|
|
||
|
|
|
||
|
|
return true;
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
void Bus_Parallel16::create_dma_desc_link(void *data, size_t size, bool dmadesc_b)
|
||
|
|
{
|
||
|
|
static constexpr size_t MAX_DMA_LEN = (4096-4);
|
||
|
|
|
||
|
|
if (dmadesc_b)
|
||
|
|
ESP_LOGI(TAG, " * Double buffer descriptor.");
|
||
|
|
|
||
|
|
if (size > MAX_DMA_LEN)
|
||
|
|
{
|
||
|
|
size = MAX_DMA_LEN;
|
||
|
|
ESP_LOGW(TAG, "Creating DMA descriptor which links to payload with size greater than MAX_DMA_LEN!");
|
||
|
|
}
|
||
|
|
|
||
|
|
if ( (_dmadesc_a_idx+1) > _dmadesc_count) {
|
||
|
|
ESP_LOGE(TAG, "Attempted to create more DMA descriptors than allocated memory for. Expecting a maximum of %d DMA descriptors", _dmadesc_count);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
volatile lldesc_t *dmadesc;
|
||
|
|
volatile lldesc_t *next;
|
||
|
|
bool eof = false;
|
||
|
|
|
||
|
|
/*
|
||
|
|
dmadesc_a[desccount-1].eof = 1;
|
||
|
|
dmadesc_a[desccount-1].qe.stqe_next=(lldesc_t*)&dmadesc_a[0];
|
||
|
|
*/
|
||
|
|
|
||
|
|
|
||
|
|
// ESP_LOGI(TAG, "Creating descriptor %d\n", _dmadesc_a_idx);
|
||
|
|
if ( (dmadesc_b == true) ) // for primary buffer
|
||
|
|
{
|
||
|
|
dmadesc = &_dmadesc_b[_dmadesc_b_idx];
|
||
|
|
|
||
|
|
next = (_dmadesc_b_idx < (_dmadesc_count-1) ) ? &_dmadesc_b[_dmadesc_b_idx+1]:_dmadesc_b;
|
||
|
|
eof = (_dmadesc_b_idx == (_dmadesc_count-1));
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
dmadesc = &_dmadesc_a[_dmadesc_a_idx];
|
||
|
|
|
||
|
|
// https://stackoverflow.com/questions/47170740/c-negative-array-index
|
||
|
|
next = (_dmadesc_a_idx < (_dmadesc_count-1) ) ? _dmadesc_a + _dmadesc_a_idx+1:_dmadesc_a;
|
||
|
|
eof = (_dmadesc_a_idx == (_dmadesc_count-1));
|
||
|
|
}
|
||
|
|
|
||
|
|
if ( _dmadesc_a_idx == (_dmadesc_count-1) ) {
|
||
|
|
ESP_LOGW(TAG, "Creating final DMA descriptor and linking back to 0.");
|
||
|
|
}
|
||
|
|
|
||
|
|
dmadesc->size = size;
|
||
|
|
dmadesc->length = size;
|
||
|
|
dmadesc->buf = (uint8_t*) data;
|
||
|
|
dmadesc->eof = 0;
|
||
|
|
dmadesc->sosf = 0;
|
||
|
|
dmadesc->owner = 1;
|
||
|
|
dmadesc->qe.stqe_next = (lldesc_t*) next;
|
||
|
|
dmadesc->offset = 0;
|
||
|
|
|
||
|
|
if ( (dmadesc_b == true) ) { // for primary buffer
|
||
|
|
_dmadesc_b_idx++;
|
||
|
|
} else {
|
||
|
|
_dmadesc_a_idx++;
|
||
|
|
}
|
||
|
|
|
||
|
|
} // end create_dma_desc_link
|
||
|
|
|
||
|
|
void Bus_Parallel16::dma_transfer_start()
|
||
|
|
{
|
||
|
|
auto dev = _dev;
|
||
|
|
|
||
|
|
// Configure DMA burst mode
|
||
|
|
dev->lc_conf.val = I2S_OUT_DATA_BURST_EN | I2S_OUTDSCR_BURST_EN;
|
||
|
|
|
||
|
|
// Set address of DMA descriptor
|
||
|
|
dev->out_link.addr = (uint32_t) _dmadesc_a;
|
||
|
|
|
||
|
|
// Start DMA operation
|
||
|
|
dev->out_link.stop = 0;
|
||
|
|
dev->out_link.start = 1;
|
||
|
|
|
||
|
|
dev->conf.tx_start = 1;
|
||
|
|
|
||
|
|
|
||
|
|
} // end
|
||
|
|
|
||
|
|
|
||
|
|
void Bus_Parallel16::dma_transfer_stop()
|
||
|
|
{
|
||
|
|
auto dev = _dev;
|
||
|
|
|
||
|
|
// Stop all ongoing DMA operations
|
||
|
|
dev->out_link.stop = 1;
|
||
|
|
dev->out_link.start = 0;
|
||
|
|
dev->conf.tx_start = 0;
|
||
|
|
|
||
|
|
} // end
|
||
|
|
|
||
|
|
|
||
|
|
void Bus_Parallel16::flip_dma_output_buffer()
|
||
|
|
{
|
||
|
|
if ( _double_dma_buffer == false) return;
|
||
|
|
|
||
|
|
if ( _dmadesc_a_active == true) // change across to everything 'b''
|
||
|
|
{
|
||
|
|
_dmadesc_a[_dmadesc_count-1].qe.stqe_next = &_dmadesc_b[0];
|
||
|
|
_dmadesc_b[_dmadesc_count-1].qe.stqe_next = &_dmadesc_b[0];
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
_dmadesc_a[_dmadesc_count-1].qe.stqe_next = &_dmadesc_a[0];
|
||
|
|
_dmadesc_b[_dmadesc_count-1].qe.stqe_next = &_dmadesc_a[0];
|
||
|
|
}
|
||
|
|
} // end flip
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
#endif
|