ScStw/ESP32-HUB75-MatrixPanel-DMA
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

Update esp32_i2s_parallel_dma.cpp

Browse source
This commit is contained in:
mrcodetastic 2024-07-21 12:18:55 +01:00
parent c55ea57458
commit 04a1727b23
1 changed files with 17 additions and 36 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

47
src/platforms/esp32/esp32_i2s_parallel_dma.cpp
View file

@ -238,8 +238,8 @@ Modified heavily for the ESP32 HUB75 DMA library by:
dev->clkm_conf.clkm_div_a = 1; // Clock denominator
dev->clkm_conf.clkm_div_b = 0; // Clock numerator
unsigned int _div_num = (freq > 8000000) ? 3:5; // 8 mhz or 13mhz (eventual output after factoring in tx_bck_div_num)
// Divider of 2 works theoretically with SRAM (22mhz output rate!)
// Output Frequency = (160Mhz / clkm_div_num) / (tx_bck_div_num*2)
unsigned int _div_num = (freq > 8000000) ? 2:4; // 20 mhz or 10mhz
/*
Page 675 of ESP-S2 TRM.
@ -276,7 +276,7 @@ Modified heavily for the ESP32 HUB75 DMA library by:
dev->sample_rate_conf.rx_bck_div_num = 2;
// ESP32 and ESP32-S2 TRM clearly say that "Note that I2S_TX_BCK_DIV_NUM[5:0] must not be configured as 1."
// Testing has revealed that setting it to 1 causes problems.
// Testing has revealed that setting it to 1 causes problems on S2.
dev->sample_rate_conf.tx_bck_div_num = 2;
// Output Frequency is now
@ -286,48 +286,29 @@ Modified heavily for the ESP32 HUB75 DMA library by:
// Calculate clock divider for Original ESP32
#else
dev->sample_rate_conf.rx_bck_div_num = 1;
// ESP32 and ESP32-S2 TRM clearly say that "Note that I2S_TX_BCK_DIV_NUM[5:0] must not be configured as 1."
// Testing has revealed that setting it to 1 causes problems.
dev->sample_rate_conf.tx_bck_div_num = 1;
// Note: clkm_div_num must only be set here AFTER clkm_div_b, clkm_div_a, etc. Or weird things happen!
// On original ESP32, max I2S DMA parallel speed is 20Mhz.
// 160Mhz is only assured when the CPU clock is 240Mhz on the ESP32...
// [esp32-hal-cpu.c:244] setCpuFrequencyMhz(): PLL: 480 / 2 = 240 Mhz, APB: 80000000 Hz
//static uint32_t pll_d2_clock = (source_freq/2) * 1000 * 1000 >> 1;
// I2S_CLKM_DIV_NUM 2=40MHz / 3=27MHz / 4=20MHz / 5=16MHz / 8=10MHz / 10=8MHz
//auto _div_num = std::min(255u, 1 + ((pll_d2_clock) / (1 + freq)));
/*
unsigned int _div_num = (unsigned int) (80000000L / freq / i2s_parallel_get_memory_width(ESP32_I2S_DEVICE, 16)); // 16 bits in parallel
if(_div_num < 2 || _div_num > 0xFF) {
// return ESP_ERR_INVALID_ARG;
_div_num = 4;
}
The clock configuration of the LCD master transmitting mode is identical to I2S’ clock configuration.
In the LCD mode, the frequency of WS is half of f-bck
*/
unsigned int _div_num = (freq > 8000000) ? 5:10; // 8 mhz or 16mhz
// ESP32 and ESP32-S2 TRM clearly say that "Note that I2S_TX_BCK_DIV_NUM[5:0] must not be configured as 1."
dev->sample_rate_conf.tx_bck_div_num = 2;
dev->sample_rate_conf.rx_bck_div_num = 2;
ESP_LOGD("ESP32", "i2s pll_d2_clock clkm_div_num is: %u", _div_num);
dev->clkm_conf.clka_en=0; // Use the 80mhz system clock (PLL_D2_CLK) when '0'
dev->clkm_conf.clka_en = 0; // Use the 80mhz system clock (PLL_D2_CLK) when '0'
dev->clkm_conf.clkm_div_a = 1; // Clock denominator
dev->clkm_conf.clkm_div_b = 0; // Clock numerator
unsigned int _div_num = (freq > 8000000) ? 2:4; // 20 mhz or 10mhz
ESP_LOGD("ESP32", "i2s pll_d2_clock clkm_div_num is: %u", _div_num);
// Frequency will be (80Mhz / clkm_div_num / tx_bck_div_num (2))
dev->clkm_conf.clkm_div_num = _div_num;
// dev->clkm_conf.clk_en=1;
// Note tx_bck_div_num value of 2 will further divide clock rate
#endif
////////////////////////////// END CLOCK CONFIGURATION /////////////////////////////////
// I2S conf2 reg