Update to include SM5266P

Attempt to resolve #164
This commit is contained in:
mrfaptastic 2021-08-16 11:01:26 +01:00
parent e6aa0cbd80
commit 11eaf34d91
2 changed files with 37 additions and 4 deletions

View file

@ -616,7 +616,15 @@ void MatrixPanel_I2S_DMA::clearFrameBuffer(bool _buff_id){
// fill all x_pixels except color_index[0] (LSB) ones, this also clears all color data to 0's black // fill all x_pixels except color_index[0] (LSB) ones, this also clears all color data to 0's black
do { do {
--x_pixel; --x_pixel;
row[x_pixel] = abcde;
if ( m_cfg.driver == HUB75_I2S_CFG::SM5266P) {
// modifications here for row shift register type SM5266P
// https://github.com/mrfaptastic/ESP32-HUB75-MatrixPanel-I2S-DMA/issues/164
row[x_pixel] = abcde & (0x18 << BITS_ADDR_OFFSET); // mask out the bottom 3 bits which are the clk di bk inputs
} else {
row[x_pixel] = abcde;
}
} while(x_pixel!=dma_buff.rowBits[row_idx]->width); } while(x_pixel!=dma_buff.rowBits[row_idx]->width);
// color_index[0] (LSB) x_pixels must be "marked" with a previous's row address, 'cause it is used to display // color_index[0] (LSB) x_pixels must be "marked" with a previous's row address, 'cause it is used to display
@ -624,9 +632,34 @@ void MatrixPanel_I2S_DMA::clearFrameBuffer(bool _buff_id){
abcde = ((ESP32_I2S_DMA_STORAGE_TYPE)row_idx-1) << BITS_ADDR_OFFSET; abcde = ((ESP32_I2S_DMA_STORAGE_TYPE)row_idx-1) << BITS_ADDR_OFFSET;
do { do {
--x_pixel; --x_pixel;
row[x_pixel] = abcde;
if ( m_cfg.driver == HUB75_I2S_CFG::SM5266P) {
// modifications here for row shift register type SM5266P
// https://github.com/mrfaptastic/ESP32-HUB75-MatrixPanel-I2S-DMA/issues/164
row[x_pixel] = abcde & (0x18 << BITS_ADDR_OFFSET); // mask out the bottom 3 bits which are the clk di bk inputs
} else {
row[x_pixel] = abcde;
}
//row[x_pixel] = abcde;
} while(x_pixel); } while(x_pixel);
// modifications here for row shift register type SM5266P
// https://github.com/mrfaptastic/ESP32-HUB75-MatrixPanel-I2S-DMA/issues/164
if ( m_cfg.driver == HUB75_I2S_CFG::SM5266P) {
uint16_t serialCount;
uint16_t latch;
x_pixel = dma_buff.rowBits[row_idx]->width - 16; // come back 8*2 pixels to allow for 8 writes
serialCount = 8;
do{
serialCount--;
latch = row[x_pixel] | (((((ESP32_I2S_DMA_STORAGE_TYPE)row_idx) % 8) == serialCount) << 1) << BITS_ADDR_OFFSET; // data on 'B'
row[x_pixel++] = latch| (0x05<< BITS_ADDR_OFFSET); // clock high on 'A'and BK high for update
row[x_pixel++] = latch| (0x04<< BITS_ADDR_OFFSET); // clock low on 'A'and BK high for update
} while (serialCount);
} // end SM5266P
// let's set LAT/OE control bits for specific pixels in each color_index subrows // let's set LAT/OE control bits for specific pixels in each color_index subrows
uint8_t coloridx = dma_buff.rowBits[row_idx]->color_depth; uint8_t coloridx = dma_buff.rowBits[row_idx]->color_depth;
do { do {

View file

@ -229,7 +229,7 @@ struct HUB75_I2S_CFG {
* Enumeration of hardware-specific chips * Enumeration of hardware-specific chips
* used to drive matrix modules * used to drive matrix modules
*/ */
enum shift_driver {SHIFTREG=0, FM6124, FM6126A, ICN2038S, MBI5124}; enum shift_driver {SHIFTREG=0, FM6124, FM6126A, ICN2038S, MBI5124, SM5266P};
/** /**
* I2S clock speed selector * I2S clock speed selector