ScStw/ESP32-HUB75-MatrixPanel-DMA
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Use PLL_F160M_CLK as clock source on S3

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This commit is contained in:
mrfaptastic 2023-01-25 22:37:52 +00:00
parent dcdd3e8cad
commit 58757c1975
3 changed files with 32 additions and 9 deletions
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src/platforms/esp32/RGB_HUB75_PINS.png Normal file
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34
src/platforms/esp32s3/gdma_lcd_parallel16.cpp
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@ -30,8 +30,8 @@
// static const char* TAG = "gdma_lcd_parallel16"; // static const char* TAG = "gdma_lcd_parallel16";
//#endif //#endif
static int _dmadesc_a_idx = 0; //static int _dmadesc_a_idx = 0;
static int _dmadesc_b_idx = 0; //static int _dmadesc_b_idx = 0;
dma_descriptor_t desc; // DMA descriptor for testing dma_descriptor_t desc; // DMA descriptor for testing
@ -98,23 +98,45 @@
//LCD_CAM.lcd_clock.clk_en = 0; // Enable peripheral clock //LCD_CAM.lcd_clock.clk_en = 0; // Enable peripheral clock
// LCD_CAM_LCD_CLK_SEL Select LCD module source clock. 0: clock source is disabled. 1: XTAL_CLK. 2: PLL_D2_CLK. 3: PLL_F160M_CLK. (R/W) // LCD_CAM_LCD_CLK_SEL Select LCD module source clock. 0: clock source is disabled. 1: XTAL_CLK. 2: PLL_D2_CLK. 3: PLL_F160M_CLK. (R/W)
LCD_CAM.lcd_clock.lcd_clk_sel = 2; LCD_CAM.lcd_clock.lcd_clk_sel = 3; // Use 160Mhz Clock Source
LCD_CAM.lcd_clock.lcd_ck_out_edge = 0; // PCLK low in 1st half cycle LCD_CAM.lcd_clock.lcd_ck_out_edge = 0; // PCLK low in 1st half cycle
LCD_CAM.lcd_clock.lcd_ck_idle_edge = 0; // PCLK low idle LCD_CAM.lcd_clock.lcd_ck_idle_edge = 0; // PCLK low idle
LCD_CAM.lcd_clock.lcd_clk_equ_sysclk = 0; // PCLK = CLK / (CLKCNT_N+1)
LCD_CAM.lcd_clock.lcd_clkcnt_n = 1; // Should never be zero
//LCD_CAM.lcd_clock.lcd_clk_equ_sysclk = 0; // PCLK = CLK / (CLKCNT_N+1)
LCD_CAM.lcd_clock.lcd_clk_equ_sysclk = 1; // PCLK = CLK / 1 (... so 160Mhz still)
if (_cfg.psram_clk_override) // fastest speed I can get PSRAM to work before nothing shows if (_cfg.psram_clk_override) // fastest speed I can get PSRAM to work before nothing shows
{ {
LCD_CAM.lcd_clock.lcd_clkm_div_num = 4; ESP_LOGI("S3", "DMA buffer is on PSRAM. Limiting clockspeed....");
LCD_CAM.lcd_clock.lcd_clkm_div_num = 10; //16mhz is the fasted the Octal PSRAM can support it seems
} }
else else
{ {
auto freq = (_cfg.bus_freq);
auto _div_num = 8; // 20Mhz
if (freq < 20000000L)
{
_div_num = 12; // 13Mhz
}
else if (freq > 20000000L)
{
_div_num = 6; // 26Mhz --- likely to have noise without a good connection
}
//LCD_CAM.lcd_clock.lcd_clkm_div_num = lcd_clkm_div_num; //LCD_CAM.lcd_clock.lcd_clkm_div_num = lcd_clkm_div_num;
LCD_CAM.lcd_clock.lcd_clkm_div_num = 3; LCD_CAM.lcd_clock.lcd_clkm_div_num = _div_num; //3;
} }
ESP_LOGI("S3", "Clock divider is %d", LCD_CAM.lcd_clock.lcd_clkm_div_num); ESP_LOGI("S3", "Clock divider is %d", LCD_CAM.lcd_clock.lcd_clkm_div_num);
ESP_LOGD("S3", "Resulting output clock frequency: %d Mhz", (160000000L/LCD_CAM.lcd_clock.lcd_clkm_div_num));
LCD_CAM.lcd_clock.lcd_clkm_div_a = 1; // 0/1 fractional divide LCD_CAM.lcd_clock.lcd_clkm_div_a = 1; // 0/1 fractional divide
LCD_CAM.lcd_clock.lcd_clkm_div_b = 0; LCD_CAM.lcd_clock.lcd_clkm_div_b = 0;

5
src/platforms/esp32s3/gdma_lcd_parallel16.hpp
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@ -157,8 +157,9 @@
gdma_channel_handle_t dma_chan; gdma_channel_handle_t dma_chan;
uint32_t _dmadesc_count = 0; // number of dma decriptors uint32_t _dmadesc_count = 0; // number of dma decriptors
// uint32_t _dmadesc_a_idx = 0;
//uint32_t _dmadesc_b_idx = 0; uint32_t _dmadesc_a_idx = 0;
uint32_t _dmadesc_b_idx = 0;
HUB75_DMA_DESCRIPTOR_T* _dmadesc_a = nullptr; HUB75_DMA_DESCRIPTOR_T* _dmadesc_a = nullptr;
HUB75_DMA_DESCRIPTOR_T* _dmadesc_b = nullptr; HUB75_DMA_DESCRIPTOR_T* _dmadesc_b = nullptr;