New Year Updates
Move ISR I2S device check to a compile time option.
This commit is contained in:
mrfaptastic
parent
41e5901805
commit
62deac6c48
6 changed files with 196 additions and 519 deletions
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@ -7,7 +7,7 @@
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#elif defined(ESP32_CXXX)
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#pragma message "Compiling for ESP32-Cx MCUs"
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#elif CONFIG_IDF_TARGET_ESP32 || defined(ESP32)
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#pragma message "Compiling for original 520kB SRAM ESP32."
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#pragma message "Compiling for original (released 2016) 520kB SRAM ESP32."
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#else
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#error "Compiling for something unknown!"
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#endif
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@ -759,6 +759,9 @@ void MatrixPanel_I2S_DMA::brtCtrlOE(int brt, const bool _buff_id){
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do {
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--x_coord;
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// clear OE bit for all other pixels
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row[x_coord] &= BITMASK_OE_CLEAR;
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// Brightness control via OE toggle - disable matrix output at specified x_coord
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if((coloridx > lsbMsbTransitionBit || !coloridx) && ((x_coord) >= brt)){
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row[x_coord] |= BIT_OE; // Disable output after this point.
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@ -774,8 +777,7 @@ void MatrixPanel_I2S_DMA::brtCtrlOE(int brt, const bool _buff_id){
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}
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}
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// clear OE bit for all other pixels
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row[x_coord] &= BITMASK_OE_CLEAR;
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} while(x_coord);
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// need to disable OE before/after latch to hide row transition
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@ -132,7 +132,6 @@
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#define ESP32_I2S_DMA_MODE I2S_PARALLEL_WIDTH_16 // From esp32_i2s_parallel_v2.h = 16 bits in parallel
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#define ESP32_I2S_DMA_STORAGE_TYPE uint16_t // DMA output of one uint16_t at a time.
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#define CLKS_DURING_LATCH 0 // Not (yet) used.
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#define ESP32_I2S_DEVICE I2S_NUM_0
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// Panel Upper half RGB (numbering according to order in DMA gpio_bus configuration)
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#define BITS_RGB1_OFFSET 0 // Start point of RGB_X1 bits
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@ -22,7 +22,6 @@
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#include <driver/gpio.h>
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#include <driver/periph_ctrl.h>
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#include <rom/gpio.h>
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#include <soc/gpio_sig_map.h>
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// For I2S state management.
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@ -47,41 +46,28 @@ volatile bool previousBufferFree = true;
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static void IRAM_ATTR irq_hndlr(void* arg) { // if we use I2S1 (default)
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#ifdef ESP32_ORIG
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//i2s_port_t port = *((i2s_port_t*) arg);
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if ( (*(i2s_port_t*)arg) == I2S_NUM_1 ) { // https://www.bogotobogo.com/cplusplus/pointers2_voidpointers_arrays.php
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//For I2S1
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/* Compiler pre-processor check. Saves a few cycles, no need to cast void ptr to i2s_port_t and then check 120 times second... */
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#if ESP32_I2S_DEVICE == I2S_NUM_0
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SET_PERI_REG_BITS(I2S_INT_CLR_REG(1), I2S_OUT_EOF_INT_CLR_V, 1, I2S_OUT_EOF_INT_CLR_S);
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} else {
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#else
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// For I2S0
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SET_PERI_REG_BITS(I2S_INT_CLR_REG(0), I2S_OUT_EOF_INT_CLR_V, 1, I2S_OUT_EOF_INT_CLR_S);
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}
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#else
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// Other ESP32 MCU's only have one I2S
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SET_PERI_REG_BITS(I2S_INT_CLR_REG(0), I2S_OUT_EOF_INT_CLR_V, 1, I2S_OUT_EOF_INT_CLR_S);
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#endif
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/*
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if ( previousBufferOutputLoopCount == 1)
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{
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// at this point, the previously active buffer is free, go ahead and write to it
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previousBufferFree = true;
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////previousBufferOutputLoopCount = 0;
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//i2s_parallel_set_previous_buffer_not_free();
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}
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else { previousBufferOutputLoopCount++; }
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*/
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previousBufferFree = true;
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// if(shiftCompleteCallback) // we've defined a callback function ?
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// shiftCompleteCallback();
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/*
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if(shiftCompleteCallback) { // we've defined a callback function ?
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shiftCompleteCallback();
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}
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*/
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} // end irq_hndlr
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// For peripheral setup and configuration
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static inline int get_bus_width(i2s_parallel_cfg_bits_t width) {
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switch(width) {
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case I2S_PARALLEL_WIDTH_8:
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@ -19,7 +19,8 @@ extern "C" {
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#include <freertos/FreeRTOS.h>
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#include <driver/i2s.h>
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#include <esp_err.h>
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#include <rom/lldesc.h>
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#include <esp32/rom/lldesc.h>
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#include <esp32/rom/gpio.h>
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// Get MCU Type and Max CLK Hz for MCU
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#include <esp32_i2s_parallel_mcu_def.h>
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@ -1,313 +0,0 @@
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/*
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* ESP32_I2S_PARALLEL_DMA (Version 3)
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*
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* Author: Mrfaptastic @ https://github.com/mrfaptastic/
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*
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* Description: Multi-ESP32 product DMA setup functions for ESP32 C3/H2 RISC-V chips
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*
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* ESP32C series doesn't support LCD mode / parallel DMA!
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*
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*/
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// Header
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#include "esp32_i2s_parallel_dma.h"
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#if defined(ESP32_CXXX)
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#include <esp_err.h>
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// Turn on and off a peripheral
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#include <driver/periph_ctrl.h>
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// GPIO
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#include <soc/gpio_periph.h>
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#include <hal/gpio_types.h>
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#include <driver/gpio.h>
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#include <driver/periph_ctrl.h>
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#include <rom/gpio.h>
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#include <soc/gpio_sig_map.h>
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// DMA Linked List Struct
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#include <soc/lldesc.h>
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#include <soc/io_mux_reg.h>
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// I2S
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#include <soc/i2s_struct.h>
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#include <soc/i2s_reg.h>
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// GDMA
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#include <soc/gdma_channel.h>
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#include <soc/gdma_periph.h>
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#include <soc/gdma_reg.h>
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#include <soc/gdma_struct.h>
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// For I2S state management.
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static i2s_parallel_state_t *i2s_state = NULL;
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// ESP32-S2,S3,C3 only has IS20
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// Original ESP32 has two I2S's, but we'll stick with the lowest common denominator.
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static i2s_dev_t* I2S = &I2S0; // Device to use for this library, change if you want.
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callback shiftCompleteCallback;
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void setShiftCompleteCallback(callback f) {
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shiftCompleteCallback = f;
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}
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volatile bool previousBufferFree = true;
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static void IRAM_ATTR gdma_irq_handler(void* arg) { // if we use I2S1 (default)
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GDMA.intr[0].clr.out_eof = 1;
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// at this point, the previously active buffer is free, go ahead and write to it
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// previousBufferFree = true;
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// if(shiftCompleteCallback) // we've defined a callback function ?
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// shiftCompleteCallback();
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// at this point, the previously active buffer is free, go ahead and write to it
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previousBufferFree = true;
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if(shiftCompleteCallback) // we've defined a callback function ?
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shiftCompleteCallback();
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} // end irq_hndlr
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// For peripheral setup and configuration
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static inline int get_bus_width(i2s_parallel_cfg_bits_t width) {
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switch(width) {
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case I2S_PARALLEL_WIDTH_8:
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return 8;
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case I2S_PARALLEL_WIDTH_16:
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return 16;
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case I2S_PARALLEL_WIDTH_24:
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return 24;
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default:
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return -ESP_ERR_INVALID_ARG;
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}
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}
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static void gpio_setup_out(int gpio, int sig) {
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if(gpio < 0) {
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return;
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}
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// Configure GPIO
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// https://github.com/espressif/esp-idf/blob/d5f58ab13551cd883e8d8478ba367b6e4543ffec/examples/peripherals/gpio/generic_gpio/main/gpio_example_main.c
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gpio_config_t io_conf = {};
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io_conf.intr_type = GPIO_INTR_DISABLE;
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io_conf.mode = GPIO_MODE_DEF_OUTPUT;
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io_conf.pin_bit_mask = (1ULL << gpio);
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io_conf.pull_down_en = 1;
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io_conf.pull_up_en = 0;
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gpio_config(&io_conf);
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// Set IOMUX to GPIO
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//gpio_iomux_out(gpio, sig, false); // ?? is sig right?
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gpio_matrix_out(gpio, sig, false, false);
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// Drive Strength to MAX
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gpio_set_drive_capability((gpio_num_t)gpio, (gpio_drive_cap_t)3);
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}
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// DMA Linked List
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// Size must be less than DMA_MAX - need to handle breaking long transfer into two descriptors before call
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// DMA_MAX by the way is the maximum data packet size you can hold in one chunk
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void link_dma_desc(volatile lldesc_t *dmadesc, volatile lldesc_t *prevdmadesc, void *memory, size_t size)
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{
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if(size > DMA_MAX) size = DMA_MAX;
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dmadesc->size = size;
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dmadesc->length = size;
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dmadesc->buf = memory;
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dmadesc->eof = 0;
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dmadesc->sosf = 0;
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dmadesc->owner = 1;
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dmadesc->qe.stqe_next = 0; // will need to set this elsewhere
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dmadesc->offset = 0;
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// link previous to current
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if(prevdmadesc)
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prevdmadesc->qe.stqe_next = (lldesc_t*)dmadesc;
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}
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esp_err_t i2s_parallel_driver_install(i2s_port_t port, i2s_parallel_config_t* cfg) {
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port = I2S_NUM_0; /// override.
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if(port < I2S_NUM_0 || port >= I2S_NUM_MAX) {
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return ESP_ERR_INVALID_ARG;
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}
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if(cfg->sample_width < I2S_PARALLEL_WIDTH_8 || cfg->sample_width >= I2S_PARALLEL_WIDTH_MAX) {
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return ESP_ERR_INVALID_ARG;
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}
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if(cfg->sample_rate > I2S_PARALLEL_CLOCK_HZ || cfg->sample_rate < 1) {
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return ESP_ERR_INVALID_ARG;
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}
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uint32_t clk_div_main = I2S_PARALLEL_CLOCK_HZ / cfg->sample_rate / i2s_parallel_get_memory_width(port, cfg->sample_width);
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if(clk_div_main < 2 || clk_div_main > 0xFF) {
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return ESP_ERR_INVALID_ARG;
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}
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// Setup GPIOs
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int bus_width = get_bus_width(cfg->sample_width);
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i2s_dev_t *i2s_dev = I2S; // There's only one I2S device on C3....
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//Figure out which signal numbers to use for routing
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//printf("Setting up parallel I2S bus at I2S%d\n", i2snum(dev));
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int sig_data_base = I2SO_SD_OUT_IDX;
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int sig_clk = I2SO_WS_OUT_IDX;
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//Route the signals
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for (int x=0; x < bus_width; x++) {
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gpio_setup_out(cfg->gpio_bus[x], sig_data_base+x);
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}
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//ToDo: Clk/WS may need inversion?
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gpio_setup_out(cfg->gpio_clk, sig_clk);
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// Power on I2S1 (or 0)
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periph_module_enable(PERIPH_I2S1_MODULE);
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// Now it's apparently I2S0 !?
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//i2s_dev_t *i2s_dev = &I2S0;
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// Reset RX (not that we use it)
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i2s_dev->rx_conf.val = 0;
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i2s_dev->rx_conf.rx_reset=1; i2s_dev->rx_conf.rx_reset=0;
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i2s_dev->rx_conf.rx_fifo_reset=1; i2s_dev->rx_conf.rx_fifo_reset=0;
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// Reset TX (what we care about)
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i2s_dev->tx_conf.val = 0;
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i2s_dev->tx_conf.tx_reset=1; i2s_dev->tx_conf.tx_reset=0;
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i2s_dev->tx_conf.tx_fifo_reset=1; i2s_dev->tx_conf.tx_fifo_reset=0;
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i2s_dev->tx_conf.tx_chan_equal=1;
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// Device setup
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i2s_dev->tx_conf1.val = 0;
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i2s_dev->tx_conf1.tx_bits_mod=16;//cfg->bits;
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i2s_dev->rx_conf1.val = 0;
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i2s_dev->rx_conf1.rx_bits_mod=16; //cfg->bits;
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i2s_dev->tx_conf1.tx_bck_div_num=2;
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i2s_dev->rx_conf1.rx_bck_div_num=2;
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i2s_dev->tx_clkm_conf.val=0;
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i2s_dev->tx_clkm_conf.tx_clk_sel=2; // 160mhz
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// clock speed
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i2s_dev->tx_clkm_conf.tx_clkm_div_num=160/16; // 10Mhz
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//i2s_dev->tx_clkm_div_conf.val = 0; //
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i2s_dev->tx_clkm_div_conf.tx_clkm_div_x = 0; // > ?
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i2s_dev->tx_clkm_div_conf.tx_clkm_div_y = 0; //
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i2s_dev->tx_clkm_div_conf.tx_clkm_div_yn1 = 0;
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i2s_dev->tx_clkm_div_conf.tx_clkm_div_z = 0;
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i2s_dev->tx_clkm_conf.tx_clk_active=1; // Start
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//Allocate DMA descriptors
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i2s_state = malloc(sizeof(i2s_parallel_state_t));
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assert(i2s_state != NULL);
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i2s_parallel_state_t *st= i2s_state;
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st->desccount_a = cfg->desccount_a;
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st->desccount_b = cfg->desccount_b;
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st->dmadesc_a = cfg->lldesc_a;
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st->dmadesc_b = cfg->lldesc_b;
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// setup I2S Interrupt
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// SET_PERI_REG_BITS(I2S_INT_ENA_REG(1), I2S_OUT_EOF_INT_ENA_V, 1, I2S_OUT_EOF_INT_ENA_S);
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// allocate a level 1 interrupt: lowest priority, as ISR isn't urgent and may take a long time to complete
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esp_intr_alloc(ETS_I2S1_INTR_SOURCE, (int)(ESP_INTR_FLAG_IRAM | ESP_INTR_FLAG_LEVEL1), gdma_irq_handler, NULL, NULL);
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GDMA.intr[0].ena.out_eof = 1; //?
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// Reset GDMA device
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GDMA.channel[0].out.out_conf0.out_rst = 1; // REG_SET_BIT(DMA_OUT_CONF0_CH0_REG, DMA_OUT_RST_CH0);
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GDMA.channel[0].out.out_conf0.out_rst = 0; // REG_CLR_BIT(DMA_OUT_CONF0_CH0_REG, DMA_OUT_RST_CH0);
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// GDMA.channel[0].out.out_conf0.out_eof_mode = 1; ?
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GDMA.misc_conf.ahbm_rst_inter = 1;
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GDMA.misc_conf.ahbm_rst_inter = 0;
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// Setup interrupt
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// Setup outlink
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GDMA.channel[0].out.out_link.addr = ((uint32_t)(&st->dmadesc_a[0]));// Set a value here
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GDMA.channel[0].out.out_peri_sel.sel = SOC_GDMA_TRIG_PERIPH_I2S0; // 3 = I2S0
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GDMA.channel[0].out.out_conf0.out_data_burst_en = 1;
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GDMA.channel[0].out.out_conf0.outdscr_burst_en = 1;
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GDMA.channel[0].out.out_link.start = 1;
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while (!GDMA.intr->raw.out_eof) { } // check status
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i2s_dev->tx_conf.tx_start = 1;
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return ESP_OK;
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}
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esp_err_t i2s_parallel_stop_dma(i2s_port_t port) {
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if(port < I2S_NUM_0 || port >= I2S_NUM_MAX) {
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return ESP_ERR_INVALID_ARG;
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}
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// Not implemented
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return ESP_OK;
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}
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esp_err_t i2s_parallel_send_dma(i2s_port_t port, lldesc_t* dma_descriptor) {
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if(port < I2S_NUM_0 || port >= I2S_NUM_MAX) {
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return ESP_ERR_INVALID_ARG;
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}
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// Not implemented
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return ESP_OK;
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}
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i2s_dev_t* i2s_parallel_get_dev(i2s_port_t port) {
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if(port < I2S_NUM_0 || port >= I2S_NUM_MAX) {
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return NULL;
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}
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return I2S; // HARCODE THIS TO RETURN &I2S0
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}
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// Double buffering flipping
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// Flip to a buffer: 0 for bufa, 1 for bufb
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void i2s_parallel_flip_to_buffer(i2s_port_t port, int buffer_id) {
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if (i2s_state == NULL) {
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return; // :-()
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}
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lldesc_t *active_dma_chain;
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if (buffer_id == 0) {
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active_dma_chain=(lldesc_t*)&i2s_state->dmadesc_a[0];
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} else {
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active_dma_chain=(lldesc_t*)&i2s_state->dmadesc_b[0];
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}
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// setup linked list to refresh from new buffer (continuously) when the end of the current list has been reached
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i2s_state->dmadesc_a[i2s_state->desccount_a-1].qe.stqe_next = active_dma_chain;
|
||||
i2s_state->dmadesc_b[i2s_state->desccount_b-1].qe.stqe_next = active_dma_chain;
|
||||
|
||||
// we're still shifting out the buffer, so it shouldn't be written to yet.
|
||||
previousBufferFree = false;
|
||||
}
|
||||
|
||||
bool i2s_parallel_is_previous_buffer_free() {
|
||||
return previousBufferFree;
|
||||
}
|
||||
|
||||
// End ESP32 original / S2, S3 check
|
||||
#endif
|
||||
|
|
@ -10,6 +10,7 @@
|
|||
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
|
||||
|
||||
#define ESP32_SXXX 1
|
||||
#define ESP32_I2S_DEVICE I2S_NUM_0
|
||||
|
||||
#define I2S_PARALLEL_CLOCK_HZ 160000000L
|
||||
#define DMA_MAX (4096-4)
|
||||
|
|
@ -18,6 +19,7 @@
|
|||
|
||||
// 2016 model that started it all, and this library. The best.
|
||||
#define ESP32_ORIG 1
|
||||
#define ESP32_I2S_DEVICE I2S_NUM_0
|
||||
|
||||
#define I2S_PARALLEL_CLOCK_HZ 80000000L
|
||||
#define DMA_MAX (4096-4)
|
||||
|
|
|
|||
Loading…
Reference in a new issue