minor fixes
This commit is contained in:
parent
04a1727b23
commit
95cda9dbb2
2 changed files with 16 additions and 22 deletions
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@ -1,7 +1,10 @@
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#include "dma_parallel_io.hpp"
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#include "dma_parallel_io.hpp"
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#include <Arduino.h>
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#ifdef CONFIG_IDF_TARGET_ESP32C6
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#ifdef CONFIG_IDF_TARGET_ESP32C6
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#pragma message "Compiling for ESP32-C6"
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//First implementation might have a lot of bugs, especially on deleting and reloading
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//First implementation might have a lot of bugs, especially on deleting and reloading
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//major test setup:
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//major test setup:
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@ -33,8 +36,6 @@
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// for a view clocks
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// for a view clocks
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// limitation of parlio interface
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// limitation of parlio interface
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// PARLIO_LL_TX_MAX_BITS_PER_FRAME = (PARLIO_LL_TX_MAX_BYTES_PER_FRAME * 8)
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// PARLIO_LL_TX_MAX_BITS_PER_FRAME = (PARLIO_LL_TX_MAX_BYTES_PER_FRAME * 8)
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// PARLIO_LL_TX_MAX_BYTES_PER_FRAME = 0xFFFF
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// PARLIO_LL_TX_MAX_BYTES_PER_FRAME = 0xFFFF
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@ -53,8 +54,6 @@
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// I don't get it
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// I don't get it
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#pragma message "Compiling for ESP32-C6"
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#pragma message "Compiling for ESP32-C6"
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#ifdef ARDUINO_ARCH_ESP32
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#ifdef ARDUINO_ARCH_ESP32
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@ -81,19 +80,14 @@ DRAM_ATTR volatile bool previousBufferFree = true;
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IRAM_ATTR bool gdma_on_trans_eof_callback(gdma_channel_handle_t dma_chan,
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IRAM_ATTR bool gdma_on_trans_eof_callback(gdma_channel_handle_t dma_chan,
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gdma_event_data_t *event_data, void *user_data)
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gdma_event_data_t *event_data, void *user_data)
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{
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{
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//esp_rom_delay_us(100);
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//esp_rom_delay_us(100);
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previousBufferFree = true;
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previousBufferFree = true;
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//parlio_ll_tx_reset_fifo(&PARL_IO);
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//parlio_ll_tx_reset_fifo(&PARL_IO);
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parlio_ll_tx_reset_clock(&PARL_IO);
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parlio_ll_tx_reset_clock(&PARL_IO);
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//gdma_start(dma_chan, (intptr_t)&_dmadesc_a[0]);
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//gdma_start(dma_chan, (intptr_t)&_dmadesc_a[0]);
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//while (parlio_ll_tx_is_ready(&PARL_IO) == false);
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//while (parlio_ll_tx_is_ready(&PARL_IO) == false);
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//parlio_ll_tx_start(&PARL_IO, true);
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//parlio_ll_tx_start(&PARL_IO, true);
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//parlio_ll_tx_enable_clock(&PARL_IO, true);
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//parlio_ll_tx_enable_clock(&PARL_IO, true);
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@ -110,6 +104,7 @@ void Bus_Parallel16::config(const config_t &cfg)
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bool Bus_Parallel16::init(void)
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bool Bus_Parallel16::init(void)
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{
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{
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ESP_LOGI("ESP32-C6", "Performing DMA bus init() for ESP-C6");
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periph_module_enable(PERIPH_PARLIO_MODULE);
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periph_module_enable(PERIPH_PARLIO_MODULE);
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periph_module_reset (PERIPH_PARLIO_MODULE);
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periph_module_reset (PERIPH_PARLIO_MODULE);
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@ -120,19 +115,18 @@ bool Bus_Parallel16::init(void)
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parlio_ll_clock_source_t clk_src = (parlio_ll_clock_source_t)PARLIO_CLK_SRC_DEFAULT;
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parlio_ll_clock_source_t clk_src = (parlio_ll_clock_source_t)PARLIO_CLK_SRC_DEFAULT;
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uint32_t periph_src_clk_hz = 0;
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uint32_t periph_src_clk_hz = 0;
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esp_clk_tree_src_get_freq_hz((soc_module_clk_t)clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &periph_src_clk_hz);
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esp_clk_tree_src_get_freq_hz((soc_module_clk_t)clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &periph_src_clk_hz);
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parlio_ll_tx_set_clock_source(&PARL_IO, clk_src);
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parlio_ll_tx_set_clock_source(&PARL_IO, clk_src);
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uint32_t div = (periph_src_clk_hz + _cfg.bus_freq - 1) / _cfg.bus_freq;
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uint32_t div = (periph_src_clk_hz + _cfg.bus_freq - 1) / _cfg.bus_freq;
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parlio_ll_tx_set_clock_div(&PARL_IO, div);
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parlio_ll_tx_set_clock_div(&PARL_IO, div);
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_cfg.bus_freq = periph_src_clk_hz / div;
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_cfg.bus_freq = periph_src_clk_hz / div;
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ESP_LOGI("C6", "Clock divider is %d", (int)div);
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ESP_LOGI("C6", "Clock divider is %d", (int)div);
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ESP_LOGD("C6", "Resulting output clock frequency: %d Mhz", (int)(160000000L / _cfg.bus_freq));
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ESP_LOGD("C6", "Resulting output clock frequency: %d Mhz", (int)(160000000L / _cfg.bus_freq));
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// Allocate DMA channel and connect it to the LCD peripheral
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// Allocate DMA channel and connect it to the LCD peripheral
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static gdma_channel_alloc_config_t dma_chan_config = {
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static gdma_channel_alloc_config_t dma_chan_config = {
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.sibling_chan = NULL,
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.sibling_chan = NULL,
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@ -99,7 +99,7 @@
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//LCD_CAM.lcd_clock.clk_en = 0; // Enable peripheral clock
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//LCD_CAM.lcd_clock.clk_en = 0; // Enable peripheral clock
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// LCD_CAM_LCD_CLK_SEL Select LCD module source clock. 0: clock source is disabled. 1: XTAL_CLK. 2: PLL_D2_CLK. 3: PLL_F160M_CLK. (R/W)
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// LCD_CAM_LCD_CLK_SEL Select LCD module source clock. 0: clock source is disabled. 1: XTAL_CLK. 2: PLL_D2_CLK. 3: PLL_F160M_CLK. (R/W)
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LCD_CAM.lcd_clock.lcd_clk_sel = 3; // Use 160Mhz Clock Source
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LCD_CAM.lcd_clock.lcd_clk_sel = 3; // Use 160Mhz Clock Source -> PLL_F160M_CLK
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LCD_CAM.lcd_clock.lcd_ck_out_edge = 0; // PCLK low in 1st half cycle
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LCD_CAM.lcd_clock.lcd_ck_out_edge = 0; // PCLK low in 1st half cycle
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LCD_CAM.lcd_clock.lcd_ck_idle_edge = 0; // PCLK low idle
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LCD_CAM.lcd_clock.lcd_ck_idle_edge = 0; // PCLK low idle
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@ -127,21 +127,21 @@
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//LCD_CAM.lcd_clock.lcd_clkm_div_num = 10; //16mhz is the fasted the Octal PSRAM can support it seems from faptastic's testing using an N8R8 variant (Octal SPI PSRAM).
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//LCD_CAM.lcd_clock.lcd_clkm_div_num = 10; //16mhz is the fasted the Octal PSRAM can support it seems from faptastic's testing using an N8R8 variant (Octal SPI PSRAM).
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// https://github.com/mrfaptastic/ESP32-HUB75-MatrixPanel-DMA/issues/441#issuecomment-1513631890
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// https://github.com/mrfaptastic/ESP32-HUB75-MatrixPanel-DMA/issues/441#issuecomment-1513631890
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LCD_CAM.lcd_clock.lcd_clkm_div_num = 12; // 13Mhz is the fastest when the DMA memory is needed to service other peripherals as well.
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LCD_CAM.lcd_clock.lcd_clkm_div_num = 12; // 13Mhz is about the fastest output from PSRAM if we want to be able to service other peripherals as well.
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}
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}
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else
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else
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{
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{
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auto freq = (_cfg.bus_freq);
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auto freq = (_cfg.bus_freq);
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auto _div_num = 20; // 8Mhzhz
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auto _div_num = 8; // 20Mhz
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if (freq < 20000000L) {
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if (freq < 20000000L) {
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_div_num = 12; // 13Mhz
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_div_num = 10; // 16Mhz
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}
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} else {
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else if (freq > 20000000L) {
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_div_num = 7; // 22Mhz --- likely to have noise without a good connection
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_div_num = 6; // 26Mhz --- likely to have noise without a good connection
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}
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}
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_div_num = 6;
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//LCD_CAM.lcd_clock.lcd_clkm_div_num = lcd_clkm_div_num;
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//LCD_CAM.lcd_clock.lcd_clkm_div_num = lcd_clkm_div_num;
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LCD_CAM.lcd_clock.lcd_clkm_div_num = _div_num; //3;
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LCD_CAM.lcd_clock.lcd_clkm_div_num = _div_num; //3;
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