Clean up clock logic
This commit is contained in:
mrfaptastic
parent
997f3840ba
commit
be2102c3bc
2 changed files with 116 additions and 90 deletions
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@ -2,13 +2,12 @@
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static const char* TAG = "MatrixPanel";
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/* this replicates same function in rowBitStruct, but due to induced inlining it might be MUCH faster when used in tight loops
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* while method from struct could be flushed out of instruction cache between loop cycles
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* do NOT forget about buff_id param if using this
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*
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* faptastic note oct22: struct call is not inlined... commenting out this additional compile declaration
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/* This replicates same function in rowBitStruct, but due to induced inlining it might be MUCH faster
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* when used in tight loops while method from struct could be flushed out of instruction cache between
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* loop cycles do NOT forget about buff_id param if using this.
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*/
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//#define getRowDataPtr(row, _dpth, buff_id) &(dma_buff.rowBits[row]->data[_dpth * dma_buff.rowBits[row]->width + buff_id*(dma_buff.rowBits[row]->width * dma_buff.rowBits[row]->color_depth)])
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#define getRowDataPtr(row, _dpth, buff_id) &(dma_buff.rowBits[row]->data[_dpth * dma_buff.rowBits[row]->width + buff_id*(dma_buff.rowBits[row]->width * dma_buff.rowBits[row]->colour_depth)])
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bool MatrixPanel_I2S_DMA::allocateDMAmemory()
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{
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@ -316,8 +315,7 @@ void IRAM_ATTR MatrixPanel_I2S_DMA::updateMatrixDMABuffer(int16_t x_coord, int16
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// Get the contents at this address,
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// it would represent a vector pointing to the full row of pixels for the specified color depth bit at Y coordinate
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//ESP32_I2S_DMA_STORAGE_TYPE *p = getRowDataPtr(y_coord, colour_depth_idx, back_buffer_id);
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ESP32_I2S_DMA_STORAGE_TYPE *p = dma_buff.rowBits[y_coord]->getDataPtr(colour_depth_idx, back_buffer_id);
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ESP32_I2S_DMA_STORAGE_TYPE *p = getRowDataPtr(y_coord, colour_depth_idx, back_buffer_id);
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// We need to update the correct uint16_t word in the rowBitStruct array pointing to a specific pixel at X - coordinate
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@ -370,8 +368,7 @@ void MatrixPanel_I2S_DMA::updateMatrixDMABuffer(uint8_t red, uint8_t green, uint
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--matrix_frame_parallel_row;
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// The destination for the pixel row bitstream
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//ESP32_I2S_DMA_STORAGE_TYPE *p = getRowDataPtr(matrix_frame_parallel_row, colour_depth_idx, back_buffer_id);
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ESP32_I2S_DMA_STORAGE_TYPE *p = dma_buff.rowBits[matrix_frame_parallel_row]->getDataPtr(colour_depth_idx, back_buffer_id);
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ESP32_I2S_DMA_STORAGE_TYPE *p = getRowDataPtr(matrix_frame_parallel_row, colour_depth_idx, back_buffer_id);
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// iterate pixels in a row
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int x_coord=dma_buff.rowBits[matrix_frame_parallel_row]->width;
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@ -422,8 +419,8 @@ void MatrixPanel_I2S_DMA::clearFrameBuffer(bool _buff_id){
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} else {
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row[x_pixel] = abcde;
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}
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} while(x_pixel!=dma_buff.rowBits[row_idx]->width);
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// ESP_LOGI(TAG, "x pixel 1: %d", x_pixel);
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} while(x_pixel!=dma_buff.rowBits[row_idx]->width && x_pixel);
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// colour_index[0] (LSB) x_pixels must be "marked" with a previous's row address, 'cause it is used to display
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// previous row while we pump in LSB's for a new row
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@ -439,6 +436,7 @@ void MatrixPanel_I2S_DMA::clearFrameBuffer(bool _buff_id){
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row[x_pixel] = abcde;
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}
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//row[x_pixel] = abcde;
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// ESP_LOGI(TAG, "x pixel 2: %d", x_pixel);
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} while(x_pixel);
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@ -31,6 +31,7 @@ static const char* TAG = "esp32_i2s_parallel_dma";
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#include <driver/periph_ctrl.h>
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#include <soc/gpio_sig_map.h>
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#include <Arduino.h> // Need to uncomment this to get ESP_LOG output on the Arduino Serial!!!!
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#include <esp_err.h>
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#include <esp_log.h>
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@ -55,7 +56,7 @@ static void IRAM_ATTR irq_hndlr(void* arg) { // if we use I2S1 (default)
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} // end irq_hndlr
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*/
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// Static
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static i2s_dev_t* getDev(int port)
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{
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#if defined (CONFIG_IDF_TARGET_ESP32S2)
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@ -65,17 +66,7 @@ static void IRAM_ATTR irq_hndlr(void* arg) { // if we use I2S1 (default)
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#endif
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}
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void Bus_Parallel16::config(const config_t& cfg)
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{
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ESP_LOGI(TAG, "Performing config for ESP32 or ESP32-S2");
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_cfg = cfg;
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auto port = cfg.port;
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_dev = getDev(port);
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}
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//#if defined (CONFIG_IDF_TARGET_ESP32S2)
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// Static
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static void _gpio_pin_init(int pin)
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{
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if (pin >= 0)
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@ -88,12 +79,19 @@ static void IRAM_ATTR irq_hndlr(void* arg) { // if we use I2S1 (default)
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}
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void Bus_Parallel16::config(const config_t& cfg)
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{
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ESP_LOGI(TAG, "Performing config for ESP32 or ESP32-S2");
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_cfg = cfg;
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auto port = cfg.port;
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_dev = getDev(port);
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}
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bool Bus_Parallel16::init(void) // The big one that gets everything setup.
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{
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ESP_LOGI(TAG, "Performing DMA bus init() for ESP32 or ESP32-S2");
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if(_cfg.port < I2S_NUM_0 || _cfg.port >= I2S_NUM_MAX) {
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//return ESP_ERR_INVALID_ARG;
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return false;
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}
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@ -101,49 +99,6 @@ static void IRAM_ATTR irq_hndlr(void* arg) { // if we use I2S1 (default)
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return false;
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}
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//auto freq = (_cfg.freq_write, 50000000u); // ?
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auto freq = (_cfg.bus_freq);
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uint32_t _clkdiv_write = 0;
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size_t _div_num = 10;
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// Calculate clock divider for ESP32-S2
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#if defined (CONFIG_IDF_TARGET_ESP32S2)
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static constexpr uint32_t pll_160M_clock_d2 = 160 * 1000 * 1000 >> 1;
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// I2S_CLKM_DIV_NUM 2=40MHz / 3=27MHz / 4=20MHz / 5=16MHz / 8=10MHz / 10=8MHz
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_div_num = std::min(255u, 1 + ((pll_160M_clock_d2) / (1 + _cfg.freq_write)));
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_clkdiv_write = I2S_CLK_160M_PLL << I2S_CLK_SEL_S
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| I2S_CLK_EN
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| 1 << I2S_CLKM_DIV_A_S
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| 0 << I2S_CLKM_DIV_B_S
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| _div_num << I2S_CLKM_DIV_NUM_S
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;
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#else
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// clock = 80MHz(PLL_D2_CLK)
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static constexpr uint32_t pll_d2_clock = 80 * 1000 * 1000;
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// I2S_CLKM_DIV_NUM 4=20MHz / 5=16MHz / 8=10MHz / 10=8MHz
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_div_num = std::min(255u, std::max(3u, 1 + (pll_d2_clock / (1 + freq))));
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_clkdiv_write = I2S_CLK_EN
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| 1 << I2S_CLKM_DIV_A_S
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| 0 << I2S_CLKM_DIV_B_S
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| _div_num << I2S_CLKM_DIV_NUM_S
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;
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#endif
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if(_div_num < 2 || _div_num > 16) {
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return false;
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}
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//ESP_LOGI(TAG, "i2s pll clk_div_main is: %d", _div_num);
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auto dev = _dev;
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volatile int iomux_signal_base;
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volatile int iomux_clock;
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@ -152,7 +107,6 @@ static void IRAM_ATTR irq_hndlr(void* arg) { // if we use I2S1 (default)
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// Initialize I2S0 peripheral
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if (_cfg.port == 0)
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{
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periph_module_reset(PERIPH_I2S0_MODULE);
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periph_module_enable(PERIPH_I2S0_MODULE);
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@ -218,19 +172,69 @@ static void IRAM_ATTR irq_hndlr(void* arg) { // if we use I2S1 (default)
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}
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}
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////////////////////////////// Clock configuration //////////////////////////////
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// Setup i2s clock
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dev->sample_rate_conf.val = 0;
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//auto freq = (_cfg.freq_write, 50000000u); // ?
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auto freq = (_cfg.bus_freq);
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// Third stage config, width of data to be written to IO (I think this should always be the actual data width?)
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dev->sample_rate_conf.rx_bits_mod = bus_width;
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dev->sample_rate_conf.tx_bits_mod = bus_width;
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uint32_t _clkdiv_write = 0;
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size_t _div_num = 10;
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dev->sample_rate_conf.rx_bck_div_num = 2;
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dev->sample_rate_conf.tx_bck_div_num = 2;
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// Calculate clock divider for ESP32-S2
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#if defined (CONFIG_IDF_TARGET_ESP32S2)
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static constexpr uint32_t pll_160M_clock_d2 = 160 * 1000 * 1000 >> 1;
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// I2S_CLKM_DIV_NUM 2=40MHz / 3=27MHz / 4=20MHz / 5=16MHz / 8=10MHz / 10=8MHz
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_div_num = std::min(255u, 1 + ((pll_160M_clock_d2) / (1 + _cfg.freq_write)));
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/*
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_clkdiv_write = I2S_CLK_160M_PLL << I2S_CLK_SEL_S
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| I2S_CLK_EN
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| 1 << I2S_CLKM_DIV_A_S
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| 0 << I2S_CLKM_DIV_B_S
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| _div_num << I2S_CLKM_DIV_NUM_S
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;
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*/
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#else
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// clock = 80MHz(PLL_D2_CLK)
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static constexpr uint32_t pll_d2_clock = 80 * 1000 * 1000;
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// I2S_CLKM_DIV_NUM 4=20MHz / 5=16MHz / 8=10MHz / 10=8MHz
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_div_num = std::min(255u, std::max(3u, 1 + (pll_d2_clock / (1 + freq))));
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/*
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_clkdiv_write = I2S_CLK_EN
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| 1 << I2S_CLKM_DIV_A_S
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| 0 << I2S_CLKM_DIV_B_S
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| _div_num << I2S_CLKM_DIV_NUM_S
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;
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*/
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#endif
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if(_div_num < 2 || _div_num > 16) {
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return false;
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}
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ESP_LOGI(TAG, "i2s pll clk_div_main is: %d", _div_num);
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dev->clkm_conf.clkm_div_b = 0; // Clock numerator
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dev->clkm_conf.clkm_div_a = 1; // Clock denominator
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#if defined (CONFIG_IDF_TARGET_ESP32S2)
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dev->clkm_conf.clk_sel = 2; // I2S_CLK_SEL Set this bit to select I2S module clock source. 0: No clock. 1: APLL_CLK. 2: PLL_160M_CLK. 3: No clock. (R/W)
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dev->clkm_conf.clk_en = 1;
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dev->clkm_conf.clkm_div_num = _div_num;
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#endif
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// Must be ESP32 original
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#if !defined (CONFIG_IDF_TARGET_ESP32S2)
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dev->clkm_conf.clka_en=0; // Use the 80mhz system clock (PLL_D2_CLK) when '0'
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dev->clkm_conf.clkm_div_num = 3; // Hard code to whatever frequency this is. 26Mhz?
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#endif
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// Clock configuration
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// dev->clkm_conf.val=0; // Clear the clkm_conf struct
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/*
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#if defined (CONFIG_IDF_TARGET_ESP32S2)
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dev->clkm_conf.clk_sel = 2; // esp32-s2 only
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@ -243,12 +247,27 @@ static void IRAM_ATTR irq_hndlr(void* arg) { // if we use I2S1 (default)
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dev->clkm_conf.clkm_div_b=0; // Clock numerator
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dev->clkm_conf.clkm_div_a=1; // Clock denominator
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*/
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// Note: clkm_div_num must only be set here AFTER clkm_div_b, clkm_div_a, etc. Or weird things happen!
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// On original ESP32, max I2S DMA parallel speed is 20Mhz.
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//dev->clkm_conf.clkm_div_num = 32;
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dev->clkm_conf.val = _clkdiv_write;
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dev->clkm_conf.clkm_div_num = 2;
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*/
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//dev->clkm_conf.val = _clkdiv_write;
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// Setup i2s clock
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dev->sample_rate_conf.val = 0;
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// Third stage config, width of data to be written to IO (I think this should always be the actual data width?)
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dev->sample_rate_conf.rx_bits_mod = bus_width;
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dev->sample_rate_conf.tx_bits_mod = bus_width;
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// Serial clock
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dev->sample_rate_conf.rx_bck_div_num = 1;
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dev->sample_rate_conf.tx_bck_div_num = 1;
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////////////////////////////// END CLOCK CONFIGURATION /////////////////////////////////
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// I2S conf2 reg
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dev->conf2.val = 0;
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@ -352,6 +371,15 @@ static void IRAM_ATTR irq_hndlr(void* arg) { // if we use I2S1 (default)
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*/
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dev->timing.val = 0;
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//dev->int_ena.out_eof = 1
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/*
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12.6.2 DMA Interrupts
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• I2S_OUT_TOTAL_EOF_INT: Triggered when all transmitting linked lists are used up.
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• I2S_OUT_EOF_INT: Triggered when rxlink has finished sending a packet
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*/
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/*
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// We using the double buffering switch logic?
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if (conf->int_ena_out_eof)
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@ -455,10 +483,10 @@ static void IRAM_ATTR irq_hndlr(void* arg) { // if we use I2S1 (default)
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void Bus_Parallel16::create_dma_desc_link(void *data, size_t size, bool dmadesc_b)
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{
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static constexpr size_t MAX_DMA_LEN = (4096-4);
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/*
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if (dmadesc_b)
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ESP_LOGI(TAG, " * Double buffer descriptor.");
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*/
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if (size > MAX_DMA_LEN)
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{
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size = MAX_DMA_LEN;
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@ -507,7 +535,7 @@ static void IRAM_ATTR irq_hndlr(void* arg) { // if we use I2S1 (default)
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dmadesc->size = size;
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dmadesc->length = size;
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dmadesc->buf = (uint8_t*) data;
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dmadesc->eof = 0;
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dmadesc->eof = eof;
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dmadesc->sosf = 0;
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dmadesc->owner = 1;
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dmadesc->qe.stqe_next = (lldesc_t*) next;
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