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41cff62e42
commit
c55ea57458
2 changed files with 2 additions and 22 deletions
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@ -257,7 +257,7 @@ struct HUB75_I2S_CFG
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HZ_10M = 8000000,
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HZ_10M = 8000000,
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HZ_15M = 16000000, // for compatability
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HZ_15M = 16000000, // for compatability
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HZ_16M = 16000000,
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HZ_16M = 16000000,
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HZ_20M = 16000000 // for compatability
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HZ_20M = 20000000 // for compatability
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};
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};
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//
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//
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@ -58,16 +58,6 @@
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return true;
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return true;
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}
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}
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// LCD end of transaction interrupt
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static void IRAM_ATTR lcd_isr(void* arg) {
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LCD_CAM.lc_dma_int_clr.lcd_trans_done_int_clr = 1;
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previousBufferFree = true;
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}
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lcd_cam_dev_t* getDev()
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lcd_cam_dev_t* getDev()
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{
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{
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return &LCD_CAM;
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return &LCD_CAM;
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@ -269,21 +259,11 @@
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gdma_set_transfer_ability(dma_chan, &ability);
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gdma_set_transfer_ability(dma_chan, &ability);
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// Enable DMA transfer callback
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// Enable DMA transfer callback
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/*
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static gdma_tx_event_callbacks_t tx_cbs = {
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static gdma_tx_event_callbacks_t tx_cbs = {
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// .on_trans_eof is literally the only gdma tx event type available
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// .on_trans_eof is literally the only gdma tx event type available
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.on_trans_eof = gdma_on_trans_eof_callback
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.on_trans_eof = gdma_on_trans_eof_callback
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};
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};
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gdma_register_tx_event_callbacks(dma_chan, &tx_cbs, NULL);
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gdma_register_tx_event_callbacks(dma_chan, &tx_cbs, NULL);
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*/
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//
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// Enable Transaction Done interrupt
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LCD_CAM.lc_dma_int_ena.lcd_trans_done_int_ena = 1;
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// Allocate a level 1 intterupt: lowest priority, as ISR isn't urgent and may take a long time to complete
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esp_intr_alloc(ETS_LCD_CAM_INTR_SOURCE, (int)(ESP_INTR_FLAG_IRAM | ESP_INTR_FLAG_LEVEL1), lcd_isr, NULL, NULL);
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// This uses a busy loop to wait for each DMA transfer to complete...
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// This uses a busy loop to wait for each DMA transfer to complete...
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