ScStw/ESP32-HUB75-MatrixPanel-DMA
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Update gdma_lcd_parallel16.cpp

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mrfaptastic 2023-04-19 01:52:16 +01:00
parent c2885498ee
commit ec290f3dba
1 changed files with 43 additions and 43 deletions
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54
src/platforms/esp32s3/gdma_lcd_parallel16.cpp
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@ -52,7 +52,7 @@
//LCD_CAM.lcd_user.lcd_start = 0;
previousBufferFree = true;
previousBufferFree = true;
return true;
}
@ -103,43 +103,43 @@
LCD_CAM.lcd_clock.lcd_ck_out_edge = 0; // PCLK low in 1st half cycle
LCD_CAM.lcd_clock.lcd_ck_idle_edge = 0; // PCLK low idle
LCD_CAM.lcd_clock.lcd_clkcnt_n = 1; // Should never be zero
LCD_CAM.lcd_clock.lcd_clkcnt_n = 1; // Should never be zero
//LCD_CAM.lcd_clock.lcd_clk_equ_sysclk = 0; // PCLK = CLK / (CLKCNT_N+1)
LCD_CAM.lcd_clock.lcd_clk_equ_sysclk = 1; // PCLK = CLK / 1 (... so 160Mhz still)
LCD_CAM.lcd_clock.lcd_clk_equ_sysclk = 1; // PCLK = CLK / 1 (... so 160Mhz still)
// https://esp32.com/viewtopic.php?f=5&t=24459&start=80#p94487
/* Re: ESP32-S3 LCD and I2S FULL documentation
* by ESP_Sprite » Fri Mar 25, 2022 2:06 am
// https://esp32.com/viewtopic.php?f=5&t=24459&start=80#p94487
/* Re: ESP32-S3 LCD and I2S FULL documentation
* by ESP_Sprite » Fri Mar 25, 2022 2:06 am
*
* Are you sure you are staying within the limits of the psram throughput? If GDMA can't fetch data fast
* enough it leads to corruption. Also keep in mind that worst case scenario, the gdma can only use half of
* the bandwidth of the psram peripheral (as it's round-robin shared with the CPUs).
*/
* enough it leads to corruption. Also keep in mind that worst case scenario, the gdma can only use half of
* the bandwidth of the psram peripheral (as it's round-robin shared with the CPUs).
*/
// Fastest speed I can get with Octoal PSRAM to work before nothing shows. Based on manual testing.
// If using an ESP32-S3 with slower (half the bandwidth) Q-SPI (Quad), then the divisor will need to be '20' (8Mhz) which wil be flickery!
// Fastest speed I can get with Octoal PSRAM to work before nothing shows. Based on manual testing.
// If using an ESP32-S3 with slower (half the bandwidth) Q-SPI (Quad), then the divisor will need to be '20' (8Mhz) which wil be flickery!
if (_cfg.psram_clk_override)
{
ESP_LOGI("S3", "DMA buffer is on PSRAM. Limiting clockspeed....");
//LCD_CAM.lcd_clock.lcd_clkm_div_num = 10; //16mhz is the fasted the Octal PSRAM can support it seems from faptastic's testing using an N8R8 variant (Octal SPI PSRAM).
// https://github.com/mrfaptastic/ESP32-HUB75-MatrixPanel-DMA/issues/441#issuecomment-1513631890
LCD_CAM.lcd_clock.lcd_clkm_div_num = 12; // 13Mhz is the fastest when the DMA memory is needed to service other peripherals as well.
// https://github.com/mrfaptastic/ESP32-HUB75-MatrixPanel-DMA/issues/441#issuecomment-1513631890
LCD_CAM.lcd_clock.lcd_clkm_div_num = 12; // 13Mhz is the fastest when the DMA memory is needed to service other peripherals as well.
}
else
{
auto freq = (_cfg.bus_freq);
auto freq = (_cfg.bus_freq);
auto _div_num = 8; // 20Mhz
if (freq < 20000000L) {
_div_num = 12; // 13Mhz
}
else if (freq > 20000000L) {
_div_num = 6; // 26Mhz --- likely to have noise without a good connection
}
auto _div_num = 8; // 20Mhz
if (freq < 20000000L) {
_div_num = 12; // 13Mhz
}
else if (freq > 20000000L) {
_div_num = 6; // 26Mhz --- likely to have noise without a good connection
}
//LCD_CAM.lcd_clock.lcd_clkm_div_num = lcd_clkm_div_num;
LCD_CAM.lcd_clock.lcd_clkm_div_num = _div_num; //3;
@ -163,7 +163,7 @@
LCD_CAM.lcd_rgb_yuv.lcd_conv_bypass = 0; // Disable RGB/YUV converter
LCD_CAM.lcd_misc.lcd_next_frame_en = 0; // Do NOT auto-frame
LCD_CAM.lcd_misc.lcd_bk_en = 1; // https://esp32.com/viewtopic.php?t=24459&start=60#p91835
LCD_CAM.lcd_misc.lcd_bk_en = 1; // https://esp32.com/viewtopic.php?t=24459&start=60#p91835
LCD_CAM.lcd_data_dout_mode.val = 0; // No data delays
LCD_CAM.lcd_user.lcd_always_out_en = 1; // Enable 'always out' mode
@ -259,7 +259,7 @@
// Enable DMA transfer callback
static gdma_tx_event_callbacks_t tx_cbs = {
// .on_trans_eof is literally the only gdma tx event type available
// .on_trans_eof is literally the only gdma tx event type available
.on_trans_eof = gdma_on_trans_eof_callback
};
gdma_register_tx_event_callbacks(dma_chan, &tx_cbs, NULL);
@ -275,8 +275,8 @@
gdma_reset(dma_chan); // Reset DMA to known state
esp_rom_delay_us(1000);
LCD_CAM.lcd_user.lcd_dout = 1; // Enable data out
LCD_CAM.lcd_user.lcd_update = 1; // Update registers
LCD_CAM.lcd_user.lcd_dout = 1; // Enable data out
LCD_CAM.lcd_user.lcd_update = 1; // Update registers
LCD_CAM.lcd_misc.lcd_afifo_reset = 1; // Reset LCD TX FIFO
@ -354,7 +354,7 @@
_dmadesc_b[_dmadesc_b_idx].dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
//_dmadesc_b[_dmadesc_b_idx].dw0.suc_eof = 0;
_dmadesc_b[_dmadesc_b_idx].dw0.suc_eof = (_dmadesc_b_idx == (_dmadesc_count-1));
_dmadesc_b[_dmadesc_b_idx].dw0.suc_eof = (_dmadesc_b_idx == (_dmadesc_count-1));
_dmadesc_b[_dmadesc_b_idx].dw0.size = _dmadesc_b[_dmadesc_b_idx].dw0.length = size; //sizeof(data);
_dmadesc_b[_dmadesc_b_idx].buffer = data; //data;
@ -380,7 +380,7 @@
_dmadesc_a[_dmadesc_a_idx].dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
//_dmadesc_a[_dmadesc_a_idx].dw0.suc_eof = 0;
_dmadesc_a[_dmadesc_a_idx].dw0.suc_eof = (_dmadesc_a_idx == (_dmadesc_count-1));
_dmadesc_a[_dmadesc_a_idx].dw0.suc_eof = (_dmadesc_a_idx == (_dmadesc_count-1));
_dmadesc_a[_dmadesc_a_idx].dw0.size = _dmadesc_a[_dmadesc_a_idx].dw0.length = size; //sizeof(data);
_dmadesc_a[_dmadesc_a_idx].buffer = data; //data;