From f0999beb513560886e85d356a8c452e9371af08a Mon Sep 17 00:00:00 2001
From: mrfaptastic <12006953+mrfaptastic@users.noreply.github.com>
Date: Fri, 19 Feb 2021 09:11:55 +0000
Subject: [PATCH] Update esp32_i2s_parallel_v2.c

---
 esp32_i2s_parallel_v2.c | 29 ++++++++++++++++++++---------
 1 file changed, 20 insertions(+), 9 deletions(-)

diff --git a/esp32_i2s_parallel_v2.c b/esp32_i2s_parallel_v2.c
index ba88f10..9527dc1 100644
--- a/esp32_i2s_parallel_v2.c
+++ b/esp32_i2s_parallel_v2.c
@@ -207,22 +207,33 @@ esp_err_t i2s_parallel_driver_install(i2s_port_t port, i2s_parallel_config_t* co
   dev->sample_rate_conf.rx_bits_mod = bus_width;
   dev->sample_rate_conf.tx_bits_mod = bus_width;
   dev->sample_rate_conf.rx_bck_div_num = 1;
-  dev->sample_rate_conf.tx_bck_div_num = 1;
+  dev->sample_rate_conf.tx_bck_div_num = 1; // datasheet says this must be 2 or greater (but 1 seems to work)
+											// note: because it's 1 here, not 2, we need to clkm_div_num = clkm_div_num * 2
 
   // No support for fractional dividers (could probably be ported from official serial i2s driver though)
-  dev->clkm_conf.val=0;				// Clear the clkm_conf struct
-  dev->clkm_conf.clka_en=0;			// Use the 160mhz system clock (PLL_D2_CLK) when '0'
-  dev->clkm_conf.clkm_div_a=1;		// Page 310 of Technical Reference Manual - Clock denominator
-  dev->clkm_conf.clkm_div_b=1;		// Page 310 of Technical Reference Manual - Clock numerator
-
+  // 
   // It's confusing, but the max output the ESP32 can pump out when using I2S *parallel* output is 20Mhz.
   // https://easyvolts.com/2018/08/14/esp32-40msps-oscilloscope-project-is-closed-and-here-is-why/
   // and https://github.com/espressif/esp-idf/issues/2251
   // Igor - "Frequencies above 20MHz do not work in I2S mode."
-  //printf("esp32_i2s_parallel_2.c > I2S clock divider is %d \n", clk_div_main*2);	
-  // 10Mhz requested will = clk_div_main of 4 for some reason, so *2 = 8, which = 80/8 = 10Mhz gpio output.
-  dev->clkm_conf.clkm_div_num = clk_div_main*2;
+  //
+  // 16bit parallel I2S = calculated clk_div_main (per line ~142) of 4
 
+  
+  dev->clkm_conf.val=0;				// Clear the clkm_conf struct
+  dev->clkm_conf.clka_en=0;			// Use the 160mhz system clock (PLL_D2_CLK) when '0'
+  dev->clkm_conf.clkm_div_b=0;		// Page 310 of Technical Reference Manual - Clock numerator
+  dev->clkm_conf.clkm_div_a=0;		// Page 310 of Technical Reference Manual - Clock denominator
+
+  //
+  // Final Mhz output = 
+  //	Output = 80000000L / tx_bck_div_num / (clkm_div_num + (clkm_div_b/clkm_div_a) )
+  
+  // Note: clkm_div_num must only be set AFTER clkm_div_b, clkm_div_a, etc. Or weird things happen!
+  // dev->clkm_conf.clkm_div_num = (clk_div_main*2)+1;
+  dev->clkm_conf.clkm_div_num=80000000L/(conf->sample_rate + 1);   
+   
+  //printf("esp32_i2s_parallel_2.c > I2S clock divider is %d \n", clk_div_main*2);	
 
   // Some fifo conf I don't quite understand 
   dev->fifo_conf.val = 0;