Backport tx fifo byte ordering fix for ESP32-WROOM-32
This commit is contained in:
mrfaptastic
parent
2f8f465cc6
commit
f5681b2983
2 changed files with 67 additions and 22 deletions
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@ -1,6 +1,5 @@
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#include <Arduino.h>
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#include "ESP32-HUB75-MatrixPanel-I2S-DMA.h"
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//#include "xtensa/core-macros.h"
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// Credits: Louis Beaudoin <https://github.com/pixelmatix/SmartMatrix/tree/teensylc>
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// and Sprite_TM: https://www.esp32.com/viewtopic.php?f=17&t=3188 and https://www.esp32.com/viewtopic.php?f=13&t=3256
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@ -484,10 +483,14 @@ void IRAM_ATTR MatrixPanel_I2S_DMA::updateMatrixDMABuffer(int16_t x_coord, int16
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* data.
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*/
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#ifndef ESP32_S2
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// We need to update the correct uint16_t in the rowBitStruct array, that gets sent out in parallel
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// 16 bit parallel mode - Save the calculated value to the bitplane memory in reverse order to account for I2S Tx FIFO mode1 ordering
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// Irrelevant for ESP32-S2 the way the FIFO ordering works is different - refer to page 679 of S2 technical reference manual
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x_coord & 1U ? --x_coord : ++x_coord;
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#endif
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uint16_t _colorbitclear = BITMASK_RGB1_CLEAR, _colorbitoffset = 0;
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if (y_coord >= ROWS_PER_FRAME){ // if we are drawing to the bottom part of the panel
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@ -661,24 +664,46 @@ void MatrixPanel_I2S_DMA::clearFrameBuffer(bool _buff_id){
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// let's set LAT/OE control bits for specific pixels in each color_index subrows
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// Need to consider the original ESP32's (WROOM) DMA TX FIFO reordering of bytes...
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uint8_t coloridx = dma_buff.rowBits[row_idx]->color_depth;
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do {
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--coloridx;
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// switch pointer to a row for a specific color index
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row = dma_buff.rowBits[row_idx]->getDataPtr(coloridx, _buff_id);
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// switch pointer to a row for a specific color index
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row = dma_buff.rowBits[row_idx]->getDataPtr(coloridx, _buff_id);
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// drive latch while shifting out last bit of RGB data
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row[dma_buff.rowBits[row_idx]->width - 2] |= BIT_LAT; // -1 pixel to compensate array index starting at 0
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//row[dma_buff.rowBits[row_idx]->width - 1] |= BIT_LAT; // -1 pixel to compensate array index starting at 0
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#ifdef ESP32_S2
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// -1 works better on ESP32-S2 ? Because bytes get sent out in order...
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row[dma_buff.rowBits[row_idx]->width - 1] |= BIT_LAT; // -1 pixel to compensate array index starting at 0
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#else
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// We need to update the correct uint16_t in the rowBitStruct array, that gets sent out in parallel
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// 16 bit parallel mode - Save the calculated value to the bitplane memory in reverse order to account for I2S Tx FIFO mode1 ordering
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// Irrelevant for ESP32-S2 the way the FIFO ordering works is different - refer to page 679 of S2 technical reference manual
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row[dma_buff.rowBits[row_idx]->width - 2] |= BIT_LAT; // -2 in the DMA array is actually -1 when it's reordered by TX FIFO
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#endif
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// need to disable OE before/after latch to hide row transition
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// Should be one clock or more before latch, otherwise can get ghosting
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uint8_t _blank = m_cfg.latch_blanking;
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do {
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--_blank;
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row[0 + _blank] |= BIT_OE;
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row[dma_buff.rowBits[row_idx]->width - _blank - 3 ] |= BIT_OE; // (LAT pulse is (width-2) -1 pixel to compensate array index starting at 0
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#ifdef ESP32_S2
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row[0 + _blank] |= BIT_OE;
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row[dma_buff.rowBits[row_idx]->width - _blank - 1 ] |= BIT_OE; // (LAT pulse is (width-2) -1 pixel to compensate array index starting at 0
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#else
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// Original ESP32 WROOM FIFO Ordering Sucks
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uint8_t _blank_row_tx_fifo_tmp = 0 + _blank;
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(_blank_row_tx_fifo_tmp & 1U) ? --_blank_row_tx_fifo_tmp : ++_blank_row_tx_fifo_tmp;
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row[_blank_row_tx_fifo_tmp] |= BIT_OE;
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_blank_row_tx_fifo_tmp = dma_buff.rowBits[row_idx]->width - _blank - 1; // (LAT pulse is (width-2) -1 pixel to compensate array index starting at 0
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(_blank_row_tx_fifo_tmp & 1U) ? --_blank_row_tx_fifo_tmp : ++_blank_row_tx_fifo_tmp;
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row[_blank_row_tx_fifo_tmp] |= BIT_OE;
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#endif
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} while (_blank);
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} while(coloridx);
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@ -741,7 +766,17 @@ void MatrixPanel_I2S_DMA::brtCtrlOE(int brt, const bool _buff_id){
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uint8_t _blank = m_cfg.latch_blanking;
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do {
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--_blank;
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row[0 + _blank] |= BIT_OE;
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#ifdef ESP32_S2
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row[0 + _blank] |= BIT_OE;
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#else
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// Original ESP32 WROOM FIFO Ordering Sucks
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uint8_t _blank_row_tx_fifo_tmp = 0 + _blank;
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(_blank_row_tx_fifo_tmp & 1U) ? --_blank_row_tx_fifo_tmp : ++_blank_row_tx_fifo_tmp;
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row[_blank_row_tx_fifo_tmp] |= BIT_OE;
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#endif
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//row[0 + _blank] |= BIT_OE;
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// no need, has been done already
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//row[dma_buff.rowBits[row_idx]->width - _blank - 3 ] |= BIT_OE; // (LAT pulse is (width-2) -1 pixel to compensate array index starting at 0
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} while (_blank);
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@ -860,8 +895,14 @@ void MatrixPanel_I2S_DMA::hlineDMA(int16_t x_coord, int16_t y_coord, int16_t l,
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int16_t _l = l;
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do { // iterate pixels in a row
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int16_t _x = x_coord + --_l;
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#ifdef ESP32_S2
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// ESP 32 doesn't need byte flipping for TX FIFO.
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uint16_t &v = p[_x];
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#else
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// Save the calculated value to the bitplane memory in reverse order to account for I2S Tx FIFO mode1 ordering
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uint16_t &v = p[_x & 1U ? --_x : ++_x];
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#endif
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v &= _colorbitclear; // reset color bits
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v |= RGB_output_bits; // set new color bits
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@ -896,8 +937,10 @@ void MatrixPanel_I2S_DMA::vlineDMA(int16_t x_coord, int16_t y_coord, int16_t l,
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blue = lumConvTab[blue];
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#endif
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// Save the calculated value to the bitplane memory in reverse order to account for I2S Tx FIFO mode1 ordering
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#ifndef ESP32_S2
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// Save the calculated value to the bitplane memory in reverse order to account for I2S Tx FIFO mode1 ordering
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x_coord & 1U ? --x_coord : ++x_coord;
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#endif
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uint8_t color_depth_idx = PIXEL_COLOR_DEPTH_BITS;
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do { // Iterating through color depth bits (8 iterations)
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@ -1,17 +1,16 @@
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#ifndef _ESP32_RGB_64_32_MATRIX_PANEL_I2S_DMA
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#define _ESP32_RGB_64_32_MATRIX_PANEL_I2S_DMA
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/***************************************************************************************/
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/* COMPILE-TIME OPTIONS - Provide as part of PlatformIO project build_flags. */
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/***************************************************************************************/
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/*******************************************************************************************
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* COMPILE-TIME OPTIONS - MUST BE PROVIDED as part of PlatformIO project build_flags. *
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* Changing the values just here won't work - as defines needs to persist beyond the scope *
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* of just this file. *
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*******************************************************************************************/
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/* Enable serial debugging of the library, to see how memory is allocated etc. */
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//#define SERIAL_DEBUG 1
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/*
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* Do NOT build additional methods optimized for fast drawing,
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* i.e. Adafruits drawFastHLine, drawFastVLine, etc...
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*/
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/* Do NOT build additional methods optimized for fast drawing,
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* i.e. Adafruits drawFastHLine, drawFastVLine, etc... */
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//#define NO_FAST_FUNCTIONS
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/* Use GFX_Root (https://github.com/mrfaptastic/GFX_Root) instead of Adafruit_GFX library.
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@ -21,7 +20,6 @@
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*/
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//#define USE_GFX_ROOT 1
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/* Physical / Chained HUB75(s) RGB pixel WIDTH and HEIGHT.
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*
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* This library has been tested with a 64x32 and 64x64 RGB panels.
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@ -87,11 +85,16 @@
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// #define NO_CIE1931
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/***************************************************************************************/
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/* Library Includes! */
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/* Core ESP32 hardware / idf includes! */
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#include <vector>
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#include <memory>
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#include "esp_heap_caps.h"
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#include "esp32_i2s_parallel_v2.h"
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#ifdef ESP32_S2
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#include "esp32-s2_i2s_parallel_v1.h"
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#else
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#include "esp32_i2s_parallel_v2.h"
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#endif
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#ifdef USE_GFX_ROOT
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#include <FastLED.h>
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@ -101,7 +104,6 @@
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#endif
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/***************************************************************************************/
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/* Definitions below should NOT be ever changed without rewriting library logic */
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#define ESP32_I2S_DMA_MODE I2S_PARALLEL_WIDTH_16 // From esp32_i2s_parallel_v2.h = 16 bits in parallel
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